CSCI 4717 -- Test 1 Study Guide

Below you will find a list of the topics that will be covered on Test 1. Included for each topic is the reading from the textbook for that topic. Last year's test is posted here to help you study.

I would look for the test to be about 60% to 70% short answer questions such as "For a fixed block size, which cache uses the most bits in a tag?" (BTW, the answer is full associative.) The remaining portion of the test will be questions longer questions such as:

The following is an exhaustive list of the topics that we've covered since the first week of class that you could see on the test.

  1. Breaking a system into components -- Week 1 lecture
    1. Hierarchical nature of complex systems
      1. All systems can be described as a tree of components
      2. Breaking system into components forces designer to understand the data that is passed between them
      3. Working with a hierarchy -- the designer need only concern themselves with the details of their level
      4. Working with a well-defined set of inputs, outputs, and function definition, designers can completely design their component without any knowledge of how rest of system is made
    2. System design
      1. When designing a system, there are two ways to design it: top-down or bottom-up
      2. Top down -- solving a problem by dividing the system into individual functions and building a component to satisfy each function.
        1. Efficient use of components
        2. Easier to meet performance goals of the system specification
        3. More expensive and time consuming
      3. Bottom up -- solving a problem using an existing system (e.g., using a PC to solve a problem)
        1. Cheaper in small quantities
        2. Design time is reduced
        3. Past experiences can be drawn upon
      4. Black boxes
        1. This is the building block of the hierarchical system design.
        2. If inputs, outputs, and functions are well defined, the designer doesn't need to know about anything above or below in the system
      5. Implementation of components
        1. Hardware (HW) -- The permanent, physical implementation of circuits and devices; hardware is required for all systems
        2. Software (SW) -- The programs contained in read/write memory ranging from machine language to high-level languages; requires a processor to run (hardware dependent)
        3. Firmware (FW) -- Lies between hardware and software; programs (usually machine code) contained in read only memory
      6. Performance characteristics
        1. Throughput/speed -- HW best; FW average; SW worst
        2. Cost -- HW average; FW average; SW worst
        3. Adaptability -- HW worst; FW average; SW best
        4. Reliability -- HW best; FW average; SW average
    3. System consists of a set of components (black boxes) and their interconnections. Therefore, the system can be described purely with:
      1. Structure -- the way in which the components are connected
      2. Function -- The operation of the component within the system
  2. Performance & single-processor architectures -- Sections 2.1, 2.2, and 3.1 through 3.3
    1. Making computers faster
      1. Basic building blocks
      2. Removing bottlenecks - Not all components have kept up
      3. Prediction
      4. Making sure no component is idle
      5. I/O Schemes
      6. Types of performance measurements and the problems with them
    2. Moore's law -- discuss the law itself along with its effects
    3. Compare and contrast the different architectural needs of different applications, e.g., what architectural features would distinguish a router from a database?
    4. von Neumann Architecture
      1. Be able to draw the von Neumann architecture (Figure 2.1) and identify purpose of components
      2. Be able to identify purpose of components in Figures 2.3 and 3.2
      3. Be able to discuss key concepts of von Neumann architecture
        1. Data and instructions in single read-write
          memory
        2. Memory contents are addressable by
          location regardless of whether content is
          data or instruction
        3. Execution of code is sequential from one
          instruction to the next unless a jump is
          encountered
    5. Structure of the IAS machine
    6. Discuss instruction cycle state diagram (Figures 3.6 and 3.12)
    7. Basic single-processor architecture (Be able to answer the questions you submitted for homework #1)
    8. Assembly language/machine code (This should reflect what you learned from the instruction decoder project)
    9. Interrupt concepts
      1. Benefits
      2. Multiple interrupts
        1. Priorities
        2. Enabling
        3. Nested vs. sequential (Figure 3.13)
  3. Memory concepts -- Ch. 4
    1. Characteristics of different types of memory with respect to their proximity to processor
      1. CPU - temporary memory or registers
      2. Internal - main memory and cache
      3. External - peripherals such as disk, tape, and networked memory devices
    2. Memory Hierarchy trade offs
    3. Locality of Reference Principle
    4. Basic cache operation
    5. Basic cache Structure
      1. Words
      2. Blocks
      3. Tags
      4. Lines
    6. Cache implementation
      1. Size
      2. Mapping Function
      3. Replacement Algorithm
      4. Write Policy
      5. Block Size
      6. Number of Caches
    7. Details of Mapping Functions -- Be sure you understand the operation of each of these functions in addition to their benefits and drawbacks
      1. Direct
      2. Full Associative
      3. Set Associative
    8. Replacement Algorithms -- Understand the purpose of these algorithms in addition to how each of the following works
      1. Least Recently used (LRU)
      2. First in first out (FIFO)
      3. Least frequently used (LFU)
      4. Random
    9. Cache Write Policies
      1. Problems with writing to caches
      2. Solutions
        1. Write through
        2. Write back
        3. Bus watching with write through
        4. Hardware transparency
        5. Noncacheable memory
    10. Multi-Level Caches
    11. Unified versus Split Caches
  4. Internal memory details & memory management -- Ch. 5
    1. Memory Cell Operation and Organization
    2. Don't worry about learning semiconductor memory types
    3. Dynamic RAM
      1. Operation (Figure 5.2a)
      2. Characteristics and applications
      3. Organization details (Figure 5.3)
        1. Rows and columns
        2. RAS and CAS
        3. Refreshing
      4. Organization to increase capacities
        1. Organization into wider data buses (Figure 5.5)
        2. Organization into larger memory spaces (Figure 5.6)
    4. Static RAM
      1. Operation (Figure 5.2b)
      2. Characteristics and applications
    5. Be sure to be able to compare and contrast SRAM & DRAM
    6. Advanced DRAM Organization
      1. Fast page mode (FPM)
      2. Extended data out (EDO)
      3. Synchronous DRAM (SDRAM and DDR-SDRAM)
      4. RAMBUS
      5. CDRAM (Cache DRAM)
  5. Error correction and detection
    1. Types of errors: hard or soft
      1. Hard Failure – Permanent defect caused by
        1. Harsh environmental abuse (including static electricity)
        2. Manufacturing defect
        3. Wear such as trace erosion
      2. Soft Error
        1. Random, non-destructive
        2. Caused by electrical or EM/radioactive glitches
        3. No permanent damage to memory
    2. Single error correction
      1. The use and implementation of check codes
      2. How to generate and use syndrome words
      3. Hamming Error Correction Code (This is the code we described using the Venn diagrams)
      4. Be able to calculate how many code bits (K) would be needed for a specific number of data bits (M)
    3. Double error detection
      1. The use of an additional parity bit to allow for double error detection
      2. Double error detection will not correct double errors, but it will see if a double error has occurred.

That's about it. Feel free to use the e-mail list on Blackboard if you have questions about topics on the test. You may find your answer quicker than if you try to e-mail me directly.