ACC

Summary:
The ACC function accumulates an input, X, to form the result, Z.  The width of the
X input can be controlled with the Xwidth  parameter.  The format (signed or unsigned) 
of X is controlled with Xsigned. The output, Z, and the accumulator have a width equal 
to Awidth.  When rounding is selected (Round>0), only the bits of Z with indices from 
Round to Awidth-1 are valid.

The accumulator is reset when R is LOW and CLK goes HIGH.


Function: 
    Z(n)=X(n-1) + (R(n-1) ? Z(n-1) : 1<<(Round-1))

Signals:
    X: Xwidth wide input (Xsigned sets format)
    Z: Awidth wide output
    R: synchronous 1-bit reset control, active LOW
    CLK: positive edge triggered clock

Parameters:
    Name: actual module name
    Xwidth: width of input X
    Awidth: width of the accumulator and output
    Xsigned: format of X (signed when selected, unsigned otherwise)
    Round: select the rounding position (0 for no rounding)
    AdderType: select the adder type ('fastcla', 'cla', 'csa', 'clsa')

Verilog Usage:  
    Name(X,Z,R,CLK);

Version: $Id: ACC.help,v 1.4 1994/09/19 22:43:23 peter Exp $