Addsub

Summary:
This functions adds or subtracts two inputs, X and Y, to form Z.  The input S controls 
whether addition or subtraction is performed.  The width of all three signals is 
controlled by Width.  The type of the adder is controlled by "AdderType".  The adder 
is always optimized for minimum possible delay.

Function:
    Z=X+Y   (S=0)
    Z=X-Y   (S=1)

Signals:
    Z: Width wide output
    X,Y: Width wide inputs
    S: 1-bit subtract control (1 for subtract, 0 for add)

Parameters:
    Name: actual module name
    Width: width of the X,Y and Z signals
    AdderType: type of the adder to build (cla, fastcla, clsa, csa)

Verilog Usage: 
    Name(X,Y,S,Z);


Version: $Id: Addsub.help,v 1.2 1994/09/19 22:43:23 peter Exp $