And, Or, Sum, Xor

Summary:
These functions perform logical AND, OR or XOR or sum on two or more inputs, X0 ..
Xn-1, to form the result Z.  AND, OR and XOR are bitwise computations across all inputs. 
The width of all signals is controlled by Width, except for Sum which has a full precision
output.  The number of inputs, n, is controlled by NumInputs. The logic is always optimized 
for minimum possible delay.

Function:
    Z=X0&X1& .. Xn-1 (bitwise And)
    Z=X0|X1| .. Xn-1 (bitwise Or)
    Z=X0+X1+ .. Xn-1 (Sum)
    Z=X0^X1^ .. Xn-1 (bitwise Xor)

Signals:
    Z: Width wide output (for Sum, width is full precision)
    Xi: Width wide inputs (0 <= i < n)

Parameters:
    Name: actual module name
	Signed: Sign mode flag (Sum only)
    NumInputs: The number, n, of input signals (2-256)
    Width: width of the signals (1-256)
	AdderType: type of final adder (Sum only, must be 'cla', 'clsa', 'csa' or 'fastcla')


Verilog Usage:  
    Name(X0, .. Xn-1,Z);


Version: $Id: And.help,v 1.5 1994/10/27 00:58:45 peter Exp $