Compare

Summary:
The Compare function performs a magnitude comparison of two inputs, X and Y, to form 
the Boolean result, Z.  Z will have a value of 1 when X>Y or X>=Y depending on X_GR_Y.  
The width of the input signals is controlled by Width.  The comparator is always 
optimized for minimum possible delay.

Function:
    Z=(X>Y) (X_GR_Y selected)
    Z=(X>=Y) (X_GR_Y deselected)

Signals:
    X,Y: Width wide inputs
    Z:   1-bit output (true if X>Y or X>=Y)

Parameters:
    Name: actual module name
    Width: width of the X,Y and Z signals (1-256)
    Signed: X and Y are signed when selected, unsigned otherwise
    X_GR_Y: compute X>Y when selected, X>=Y otherwise

Verilog Usage:  
    Name(X,Y,Z);

Version: $Id: Compare.help,v 1.3 1994/09/19 22:43:23 peter Exp $