FIFO

Summary:
This function provides physical RAM based first-in first-out (FIFO) buffers.
Both synchronous and asynchronous FIFOs are supported.  The FIFO consists
of a write port for putting data into the RAM, and a read port for extracting
data from the RAM.  In synchronous mode CLK is used to clock both the
read port and the write port.  In asynchronous mode CLKRD is used to clock
the read port, and CLKWR is used to clock the write port.  The FIFO has some
basic inputs used to control the reading and writing of the RAM, but all
of the low level RAM interfacing is managed internally.  All of the status
information needed to utilize a FIFO in a system is provided at the FIFO outputs.

Both Low-Power and High-Speed RAMs are supported as the core of the FIFO.
The FIFO depth (the maximum number of values which can be stored in the
FIFO)  is limited by the range of depths available for the RAM.  The width
of the FIFO is limited by the range of widths available for the RAM.

The user can control both the aspect ratio and the output drive strength of the
RAM used in the FIFO. The aspect ratio of the RAM, "Cdr", can be set to -1 to let
DPE choose the best value based on the optimization criterion.  If the drive
strength, "Drive", is set to -1, DPE will choose one based upon the optimization
criterion and the output loading.

See the Memory Architect User Guide for a description of the RAMs used in
this function.

Detailed timing parameters for the physical RAM used can by found in the
datasheet produced by DPE.  The datasheet can be seen by using the
"View/Datasheet" menu.

Function:
   FIFO
       See the Memory Architect User Guide for a more detailed description of the
       FIFO functions and their parameters.

Synchronous Mode Signals:
   DO:           data output
   DI:           data input
   WR:           Active HIGH write enable
   RD:           Active HIGH read enable
   OVF:          Active HIGH overflow error flag
   UNF:          Active HIGH underflow error flag
   VALID:        Number of valid words currently in the FIFO
   INVALID:      Number of invalid words currently in the FIFO
   FULL:         Active HIGH current FIFO fullness status
   EMPTY:        Active HIGH current FIFO emptiness status
   RESET_N:      Active LOW reset signal.  Must be synchronous to CLK.
   RDSTALL:      Active HIGH stall control signal for the read port (optional)
   WRSTALL:      Active HIGH stall control signal for the write port (optional)
   CLK:          Positive edge clock input

Asynchronous Mode Signals:
   DO:           Width wide data output              (CLKRD clock domain)
   DI:           Width wide data input               (CLKWR clock domain)
   WR:           Active HIGH write enable            (CLKWR clock domain)
   RD:           Active HIGH read enable             (CLKRD clock domain)
   OVF:          Active HIGH overflow error flag     (CLKWR clock domain)
   UNF:          Active HIGH underflow error flag    (CLKRD clock domain)
   RESETWR_N:    Active LOW reset signal synchronous to CLKWR
   RESETRDWR_N:  Active LOW reset signal.  Must be RESETRD_N synchronized to
                 CLKWR clock domain.
   RESETRD_N:    Active LOW reset signal synchronous to CLKRD
   RESETWRRD_N:  Active LOW reset signal.  Must be RESETWR_N synchronized to
                 CLKRD clock domain.
   VALIDWR:      Number of valid words currently in the FIFO         (CLKWR domain)
   INVALIDWR:    Number of invalid words currently in the FIFO       (CLKWR domain)
   FULLWR:       Active HIGH current FIFO fullness status            (CLKWR domain)
   EMPTYWR:      Active HIGH current FIFO emptiness status           (CLKWR domain)
   VALIDRD:      Number of valid words currently in the FIFO         (CLKRD domain)
   INVALIDRD:    Number of invalid words currently in the FIFO       (CLKRD domain)
   FULLRD:       Active HIGH current FIFO fullness status            (CLKRD domain)
   EMPTYRD:      Active HIGH current FIFO emptiness status           (CLKRD domain)
   RDSTALL:      Active HIGH stall control signal for the read port  (optional, CLKRD)
   WRSTALL:      Active HIGH stall control signal for the write port (optional, CLKWR)
   CLKWR:        Positive edge clock input for the write port
   CLKRD:        Positive edge clock input for the read port

Parameters:
   Name:         actual module name
   Width:        the bit width of the FIFO
   Len:          the word depth of the FIFO
   Cdr:          the column decode ratio for the physical RAM (1, 4, 8, 16, -1 (auto))
   Drive:        the output drive strength for the physical RAM (1, 2, 4, -1 (auto))
   Sync:         synchronous mode: 0=asynchronous, 1=synchronous
   Delay:        the overall delay goal for the FIFO
   LowPowerRAM:  Low-Power RAM mode: 0=High-Speed, 1=Low-Power
   HalfCycleRD:  half cycle read mode: 0=full cycle read, 1=half cycle read
   RdStallMode:  read stall mode: 0=no read stall, 1=stall read address and UNF only,
                 2=stall read address, UNF, and read port chip select
   WrStallMode:  write stall mode: 0=no write stall, 1=stall write this cycle,
                 2=stall write next cycle
   WaddrDelay:   delay goal for write address
   WrClkFallTime:write clock fall time
   RdCycle:      read cycle (only used for asynchronous mode)
   WrCycle:      write cycle (only used for asynchronous mode)
   RdSyncDepth:  the synchronization depth for the CLKRD clock domain
   WrSyncDepth:  the synchronization depth for the CLKWR clock domain

Synchronous Mode Verilog Usage:
   Name(DO,DI,WR,RD,OVF,UNF,VALID,INVALID,FULL,EMPTY,RESET_N,
       RDSTALL,WRSTALL,CLK);

Asynchronous Mode Verilog Usage:
   Name(DO,DI,WR,RD,OVF,UNF,RESETWR_N,RESETRDWR_N,RESETRD_N,
       RESETWRRD_N,VALIDWR,INVALIDWR,FULLWR,EMPTYWR,VALIDRD,
       INVALIDRD,FULLRD,EMPTYRD,RDSTALL,WRSTALL,CLKWR,CLKRD);

Version: $Id: FIFO.help,v 1.5 1995/07/27 18:32:30 gil Exp $