MAC, MACCS

Summary:
The MAC and MACCS functions multiply two inputs, X and Y, and sum the product with
an accumulator to form the result, Z.  The width of the X and Y inputs can be controlled 
independently with the Xwidth and Ywidth parameters, respectively.  The formats 
(signed or unsigned) of X and Y are also controlled independently with Xsigned and 
Ysigned, respectively.  The type of the multiplier (Booth or non-Booth) is controlled 
by "Booth".  The multiplier desired delay is controlled via the Delay parameter.  
When Delay is greater than zero, a pipelined multiplier is constructed, else an 
unpipelined multiplier is constructed.

MAC provides a direct multiplier-accumulator in which the carry-propagate adder is
inside the accumulator loop.  The MACCS moves the carry-propagate adder outside the
accumulator loop.  In general, MACCS will achieve higher clock frequencies with a
greater area.

The output, Z, is always a full precision value, with width equal to Awidth.  When
rounding is selected (Round>0), only the bits of Z with indices from Round to Awidth-1 
are valid.

Booth multipliers are most efficient when X and Y are large (greater than 8 bits) and 
when X and Y have an even number of bits and are signed. Non-Booth multipliers are 
most efficient when X and Y are unsigned and/or the widths are small.

The type of the final adder is controlled by "AdderType". 

Function: 
    Z(n)=X(n-1)*Y(n-1) + (R(n-1) ? Z(n-1) : 1<<(Round-1))

Signals:
    X: Xwidth wide input (Xsigned sets format)
    Y: Ywidth wide input (Ysigned sets format)
    Z: Awidth wide output
    R: synchronous 1-bit reset control, active LOW
    CLK: positive edge triggered clock

Parameters:
    Name: actual module name
    Xwidth: width of input X
    Width: width of input Y
    Awidth: width of the accumulator (must be at least XWidth+Ywidth+1 for MACCS)
    Xsigned: format of X (signed when selected, unsigned otherwise)
    Ysigned: format of Y (signed when selected, unsigned otherwise)
    Delay: select the pipelined cycle time in ps, or 0 for unpipelined
    Booth: select for a Booth multiplier, non-Booth otherwise
    AdderType: type of the adder to build (cla, fastcla, clsa, csa, ripple)
    Round: select the rounding position (0 for no rounding)

Verilog Usage:  
    Name(X,Y,Z,R,CLK);

Version: $Id: MACCS.help,v 1.1 1998/08/22 00:40:13 tino Exp $