MultConst

Summary:
The MultConst function multiplies a variable input, X by a constant Yval, to form the 
product Z.  The width of the X input can be controlled with the Xwidth parameters.  
The format (signed or unsigned) of X is controlled with Xsigned.  The multiplier
desired delay is controlled via the Delay parameter.  When Delay is greater than zero, 
a pipelined multiplier is constructed, else an unpipelined multiplier is constructed.

The output, Z, is always a full precision value, with width equal to Xwidth+width(Yval).
When rounding is selected (Round>0), only the bits of Z with indices from Round to 
Xwidth+width(Yval)-1 are valid.

The type of the final adder is controlled by "AdderType". 

Function: 
    Z=X*Yval

Signals:
    X: Xwidth wide input (Xsigned sets format)
    Z: Xwidth+width(Yval) wide output
    CLK: positive edge triggered clock (if pipelined)

Parameters:
    Name: actual module name
    Xwidth: width of input X
    Yval: 32-bit signed decimal constant value of Y (signed integer)
    Xsigned: format of X (signed when selected, unsigned otherwise)
    Delay: select the pipelined cycle time in ps, or 0 for unpipelined
    AdderType: type of the adder to build (cla, fastcla, clsa, csa, ripple)
    Round: select the rounding position (0 for no rounding)

Verilog Usage: 
    Name(X,Z); (not pipelined)
    Name(X,Z,CLK); (pipelined)


Version: $Id: MultConst.help,v 1.4 1997/06/26 20:16:34 peterr Exp $