Multiplier

Summary:
The Multiplier function multiplies two inputs, X and Y, to form the product Z.  The
width of the X and Y inputs can be controlled independently with the Xwidth and Ywidth 
parameters, respectively.  The formats (signed or unsigned) of X and Y are also 
controlled independently with Xsigned and Ysigned, respectively.  The multiplier
desired delay is controlled via the Delay parameter.  When Delay is greater than zero, 
a pipelined multiplier is constructed, else an unpipelined multiplier is constructed.

The output, Z, is always a full precision value, with width equal to Xwidth+Ywidth.
When rounding is selected (Round>0), only the bits of Z with indices from Round to 
Xwidth+Ywidth-1 are valid.

The type of the multiplier (Booth or non-Booth) is controlled by Booth.  Booth 
multipliers are most efficient when X and Y are large (greater than 8 bits) and when X
and Y have an even number of bits and are signed. Non-Booth multipliers are most 
efficient when X and Y are unsigned and/or the widths are small.

The type of the final adder is controlled by "AdderType".

Function: 
    Z=X*Y

Signals:
    X: Xwidth wide input (Xsigned sets format)
    Y: Ywidth wide input (Ysigned sets format)
    Z: Xwidth+Ywidth wide output
    CLK: positive edge triggered clock (if pipelined)

Parameters:
    Name: actual module name
    Xwidth: width of input X
    Ywidth: width of input Y
    Xsigned: format of X (signed when selected, unsigned otherwise)
    Ysigned: format of Y (signed when selected, unsigned otherwise)
    Delay: select the pipelined cycle time in ps, or 0 for unpipelined
    Booth: select for a Booth multiplier, non-Booth otherwise
    Round: select the rounding position (0 for no rounding)
    AdderType: type of the adder to build (cla, fastcla, clsa, csa, ripple)

Verilog Usage: 
    Name(X,Y,Z); (not pipelined)
    Name(X,Y,Z,CLK); (pipelined)


Version: $Id: Multiplier.help,v 1.6 1998/08/22 00:28:43 peter Exp $