Neg

Summary:
This function conditionally negates the input X based on the control signal S to form Z.
The width of X and Z is controlled by Width.  The type of the adder is controlled by 
AdderType.  The adder is always optimized for minimum possible delay.

Function:
    Z= S ? -X : X

Signals:
    Z: Width wide output
    X: Width wide signed input
    S: 1-bit wide negation control input (HIGH for -X)

Parameters:
    Name: actual module name
    Width: width of the X,Y and Z signals
    AdderType: type of the adder to build (cla, fastcla, clsa, csa)

Verilog Usage: 
    Name(X,S,Z);

Version: $Id: Neg.help,v 1.3 1994/09/19 22:43:23 peter Exp $