ShiftLR

Summary:
This function shifts the input, X, to form the result, Z.  The type of shift
performed is determined by the LEFT (left or right) and LOG (arithmetic
or logical) inputs.  Arithmetic right shifts are sign extended while logical
shifts are zero extended. The number of bits to shift X is supplied by the 
input, S. The width of X and Z is controlled by Width.  The width of S is 
chosen automatically to allow full shifting of X 
(width(S)=ceil(log2(width(X)))). The logic is always optimized for minimum 
possible delay.

Function:
    Z=LEFT ? X<<S : X>>S;

Signals:
    Z: Width wide  output
    S: shift input (width chosen automatically)
    X: Width wide input
	LEFT: 1-bit direction input (TRUE for left)
	LOG: 1-bit mode input (TRUE for logical shift, FALSE for arithmetic shift,
           ignored for LEFT TRUE)

Parameters:
    Name: actual module name
    Width: width of the X and Z signals

Verilog Usage:  
    Name(X,S,Z,LEFT,LOG);

Version: $Id: ShiftLR.help,v 1.1 1994/12/06 23:32:48 peter Exp $