ShiftReg

Summary:
This function provides physical RAM based shift registers for good density 
for long shift registers.  Each time CLK goes HIGH and the SHIFT input is HIGH, 
a value on the DI input is clocked into the shift register and a value is 
clocked out on the DO output.  When SHIFT is LOW, the shift register is inactive
and the RAM is placed in a power-down state.  The length of the shift register 
can be changed dynamically via the LEN input.  

Both asynchronous and synchronous RAMs are supported as the core of the shift 
register.  Shift register lengths are limited by the range of the number of 
words available for the RAM.  The asynchronous based shift registers have the 
greatest range of lengths due to the use of both low-power (small word sizes) 
and high-density (larger word sizes) architectures.  The width of the shift 
register is limited by the range of widths available for the RAM.

Asynchronous RAMs (high density or low power) are used in shift registers 
which have a cycle delay resolution of 1 cycle.  One read and one write 
operation are performed in each cycle, with reads occurring during CLK HIGH and 
writes during CLK LOW.  Therefore, the access time (taa) must be less than the 
CLK HIGH time and the write cycle time must be less than the CLK LOW time. The 
physical RAM has a word width determined by Width while the number of words is 
determined by MaxLen-2.  

Synchronous RAMs are used in shift registers with a delay resolution of two 
cycles because the read and write operations are performed in alternate cycles. 
The physical RAM has a word width determined by 2*Width while the number of 
words is determined by (MaxLen-3)/2.

The user can control both the aspect ratio and the output drive strength of the 
RAM used in the shift register. The aspect ratio of the RAM, Cdr, can be set to 
-1 to let DPE choose the best value based on the optimization criterion.  If the
drive strength, Drive, is set to -1, DPE will choose one based upon the 
optimization criterion and the output loading.

See the Memory Architect User Guide for a description of the RAMs used in this 
function.

Detailed timing parameters for the physical RAM used can by found in the 
datasheet in the "View/Datasheet" menu.

Note: the output of the shift register may be invalid for up to MaxLen cycles 
each time LEN is changed.

Function:
    Shift Register  
    DO(n)=DI(n-(LEN+2))  (asynchronous)
    DO(n)=DI(n-(LEN+4))  (synchronous)

Signals:
    DO:    Width wide data output
    DI:    Width wide data input
    SHIFT: Shift control, active HIGH.  Shift the data when HIGH, power down 
           the RAM when LOW 
    LEN:   Length control.  The actual shift register length = LEN+2 (async) or 
           LEN+4 (sync). The LSB of LEN is ignored for synchronous RAMs.
    RESET: Reset control, active LOW.  Must go LOW for one cycle to initialize 
           the shift register.  Shift should go HIGH when RESET is LOW.
    CLK:   Positive edge clock.  Data is shifted on each rising edge if SHIFT 
           is HIGH.

Parameters:
    Name:   actual module name
    MaxLen: the maximum shift register length)
    Width:  the width of the shift register
    Cdr:    the column decode ratio (1, 4, 8, 16, -1 (auto))
    Drive:  the output drive strength (1, 2, 4 or -1 (auto))
    Sync:   select for synchronous RAMs, deselect for asynchronous

Verilog Usage: 
    Name(DO,DI,SHIFT,RESET,LEN,CLK);  

$Id: ShiftReg.help,v 1.2 1995/04/30 12:26:34 peter Exp $