nR1W_RAM

Summary:
These functions provide physical low-power asynchronous memories (RAMs) 
with 1 to 5 ports.  All RAMs have only one write port.
The number of words and bits can be chosen in addition to the drive strength
of the outputs.  

The write port is always controlled by the highest numbered address. 

Detailed timing parameters for the physical RAM used can by found in the
datasheet in the "View/Datasheet" menu.

The RegFile function should be used to construct RAMs with very small number
of words or bits or when more than one write port is required.

Function:
    Low Power Asynchronous RAM (see Memory Architect User Manual for details)

Signals:
    DOi: Bits wide data outputs for port i
    DIi: Bits wide data input for port i
    Ai: Address input for port i 
    WEN: 1-bit Write Enable (LOW to write)
    CSN: 1-bit Chip Select (LOW to enable, HIGH to disable)

Parameters:
    Name: actual module name
    Ports: the number of total ports (5-max)
    Words: the number of words (1-128)
    Bits:  the number of bits (1-128)

Verilog Usage: 
    Name(DIn,A1,..,An,WEN,CSN,DO1,..,DOn-1); 

Version: $Id: nR1W_RAM.help,v 1.2 1996/06/06 18:09:42 peter Exp $