nRW_RAM

Summary:
These functions provide physical high-density and low-power synchronous and
asynchronous memories (RAMs) with 1 to 2 ports.  All RAM ports operate
in a read/write mode.  The number of words and bits can be chosen.

Detailed timing parameters for the physical RAM used can by found in the
datasheet in the "View/Datasheet" menu.

The nR1W_RAM function should be used for medium sized asynchronous RAMs.

The nR1W_Latch function should be used to construct RAMs with very small number
of words or bits or when more than one write port is required.

Function:
    High Density or Low Power RAM (see Memory Architect User Manual for details)

Signals:
    DOi: Bits wide data outputs for port i
    DIi: Bits wide data input for port i
    Ai: Address input for port i 
    RWNi: 1-bit Read-Write Control for port i (LOW to write, HIGH to read)
    CSNi: 1-bit Chip Select  for port i(LOW to enable, HIGH to disable)

Parameters:
    Name: actual module name
    Ports: the number of total ports (1-2)
    Words: the number of words (depends on Ports, etc)
    Bits:  the number of bits (depends on Ports, etc)
    Sync:  select for synchronous RAMs, deselect for asynchronous

Verilog Usage: 
    Name(DI,A,RWN,CSN,DO);  (1-port, async)
    Name(DI1,DI2,A1,A2,RWN1,RWN2,CSN1,CSN2,DO1,DO2); (2-port, async)
    Name(DI,A,RWN,CSN,DO,CLK);  (1-port, sync)

Version: $Id: nRW_RAM.help,v 1.2 1996/06/06 18:09:42 peter Exp $