nRmW_FF

Summary:
These functions provide netlist based low-power synchronous memories (RAMs) 
with 1 to 8 read ports and 1 to 3 write ports.  The number of words and bits
can be selected for each RAM.  To resolve write conflicts (more than one
port writing to the same address), the write ports are each assigned a priority
which decreases with the port number. The port with the highest priority 
attempting to write into the memory succeeds.  All lower-priority ports
writing to the same address are ignored.

All write operations are synchronous with CLK rising edge while all read
operations are asynchronous.  To make read operations synchronous, the
read address can be latched with a flip-flop.

Some timing parameters for the RAM can by found in the timing parameters
section of the report file.

Function:
    Low Power Synchronous RAM (see Memory Architect User Manual for details)

Signals:
    DOi: Bits wide data outputs for port i
    DIi: Bits wide data input for port i
    Ai: Address input for port i 
    WENi: 1-bit Write Enable (LOW to write)
    CSN: 1-bit Chip Select (LOW to enable, HIGH to disable)

Parameters:
    Name: actual module name
    PortsW: the number of write ports, n (1-3)
    PortsP: the number of read ports, m (1-8)
    Words: the number of words (2-128)
    Bits:  the number of bits (1-128)

Verilog Usage: 
    Name(DIm+1,..,DIn+m,A1,...,An+m,WENm+1,...,WENm+n,CSN,DO1,..DOm,CLK);  

Version: $Id: nRmW_FF.help,v 1.1 1995/06/13 00:37:54 peter Exp $