Physical ALF/OPEF/OLA meeting Feb. 1, 2000

Nancy Nettleton		Sun
John Peters		Philips
Tim Jennings		Philips
Antonio Lagnada		LSI Logic
Anand Sethuram		LSI Logic
Dhaval Sejpal		IBM
John Beatty		IBM
Joe Morrell		IBM
Paul Zuchowski		IBM
Tim Baldwin		Cadence
Tom Belpasso		Cadence
Simon Favre		Monterey
Wolfgang Roethig	NEC
Jay Abraham		SI2
Priti Vijayvargiya	Synopsys
Joe Daniels		Intrinsix

1) Review of proposal for common OPEF/ALF/OLA roadmap - Wolfgang

Amendments to the original proposal were made.
The following new paragraphs were added.

- Recommendation to form an architectural steering committee
  composed of ASIC, EDA, System companies to get industry-wide
  support

- Define a relationship with SIPPS based on requirements for
  technology representation

The group endorsed the amended proposal with 15 votes in favor,
1 abstention.

Both the original proposal and the amended proposal are attached
as separate documents. 

A.I. Send the amended proposal as a recommendation to OVI board - Wolfgang Roethig

A.I. Invite Don Cottrell for SIPPS presentation next meeting - Jay Abraham

2) Review of LEF/IDM/ALF xreference - Paul Zuchowski

* MacroClass/DefBox/PLACEMENT_TYPE
The following values are proposed:
"Ring"	block with build-in power ring, power router connects
"Pad"	IO
"Core"	core cell
"Block"	hierarchical block
MacroClass used by placer and power router
A.I. find out Cadence requirements for MacroClass - Tom Belpasso
A.I. find out IBM requirements for MacroClass - Paul Zuchowski

* EEQ, LEQ
EEQ (Electrical Equivalent) not widely used any more.
LEQ (Logical Equivalent) belongs into the synthesis domain.
ALF uses the more general concept of RESTRICT_CLASS and SWAP_CLASS.
A.I. write application note for use of RESTRICT_CLASS, SWAP_CLASS - Wolfgang
     (according to Atilla Kovacs, NEC does not use EEQ any more)

* Source
does not belong in physical library

* ClockType
does not belong in physical library, look into timing library

* OriginX, OriginY
These parameters are used for layout representation with origin
in the lower left corner of bounding box.
The group recommends not to use this concept, but to use
a self-defining origin (coordinates 0/0). This will also
affects transformations such as rotation, flip etc.
The bounding box concept requires distinction "border" (i.e. exact form)
and "extend" (i.e. bounding box) of cell. Rectangular bounding boxes
may not be sufficient for advanced layout applications.

A.I. enumerate required shapes for "border" and "extend" of block - Joe Morrell

* Site
Joe Morell presented IDM (IBM Data Dodel)
[ Paul, please fill in your notes and conclusions ]

* Obstruction/Blockage
Abstraction of spacing rules required to describe accessability
of pins within blockages. Today's layout tools sometimes "assume"
that a pin is accessible, if the distance between pin and blockage
boundary is less than a grid.
Need to support general polygons as blockages.

A.I. Propose abstract spacing rules or blockage - Wolfgang Roethig

3) Review of design rules for nanometer technology - Simon Favre

Simon's memo contains 6 examples with Wolfgang's comments.

Example 1)
Table-based models require new annotation to specify the interpolation.
Proposal: INTERPOLATION = linear | floor | ceiling

Example 2)
Need qualifier for PATTERN.
Proposal SHAPE = end | corner | jog | cross | tee | line
Default SHAPE is "line".
Need also keyword for prohibited patterns.

Example 3)
Revisit description language for basic vias.
More discussion by email needed.

Example 4)
Defered to next meeting

Example 5)
Description simple, implication on tools significant

Example 6)
Need discussion on basic geometry description (see also example 3)

A.I. Develop TEMPLATE-based viarule example - Wolfgang

A.I. Discuss open issues in teleconference next week - all