Minutes of the ALF work group meeting,
March 19 @ IVC/VIUF

Attendees:
	Mike Andrews		Mentor Graphics
	Sanjay Churiwala	Cadworx
	Tim Ehrler		VLSI Technologies
	Vassilios Gerousis	Motorola
	Kevin Grotjohn		LSI Logic
	Wolfgang Roethig	NEC
	Cary Wei		Fujitsu

Topics:

* Required features for sample library in OLA project

	Mike established requirements for DFT.
	Tim requested a set of features in a standard include file.
	Mike and Mitch Heins from Ambit will elaborate on Synthesis
	requirements in the OLA meeting March 24-25.

* Corrections to ALF spec.

	Tim gave a comprehensive list of requested corrections 
	based on internal ALF parser development at VLSI Technologies.
	Wolfgang will communicate the corrections, which have been
	approved by the work group, to the technical editor of OVI.

	The group feels that the pragmatic way of identifying and
	correcting issues has worked very well so far, and no formal
	voting is required which would slow down the process.
	Formal voting will be only required for the next version
	release (i.e. ALF1.1).

* Openness of OLA work group

	The number of participants in OLA is practically fixed
	due to the tight time schedule of delivering a prototype
	for DAC.
	However, OLA is open to observers (meeting minutes,
	specification docs on web).
	Right now, the 7 ASIC council member companies (IBM, LSI, Lucent,
	Motorola, NEC, TI, VLSI), Mentor Graphics, Ambit, Synopsys
	are OLA participants. Call for participation was also issued to
	Cadence and Avant!
	Commitment of certain deliverables and/or funding is required
	for participants.
	Exact conditions for participation are being outlined
	in the OLA meeting March 24-25.

* Feedback on ALF from ECSI

	Wolfgang presented foils from ECSI chairman Dr. Jean Mermet.
	OMILIBRES (OMI Library Representation Standards) team conducted
	survey amongst project partners, i.e.
	EDA vendors:  	Compass, Mentor Graphics, Viewlogic
	System houses:	Alcatel Bell, Ericson, Italtel, Nokia, Philips,
			SIDSA, Telefonica I&D, Thomson-CSF
	ASIC foundries:	Alcatel Mietec, Ericson, Philips, TI, VLSI Tech.

	Requirements:	mandatory support of Synthesis, Static Timing,
			Fault simulation, Floorplanning
			optional support of Power Analysis (major req.),
			formal verification, HW/SW codesign, IP (wait for VSI)

	Assessment:	ALF syntax is elegant, single format is nice feature

	Suggestions:	1. add floorplan support
			2. add IP (compiled models?)
			3. proceed with ALF-DCL harmonization
			4. build bridge with Synopsys
			5. encourage EDA vendors and ASIC vendors
			   to participate proactively

	We think that 1. is addressed in the ALF work group,
	2. needs to be discussed with VSI,
	3., 4. and 5. are addressed in the OLA work group. 


* Action items

	Mike:		work with Mitch Heins and Synopsys representative on synthesis requirements
	Mike:		distribute requirements for fault model in DFT to OLA work group
	Tim:		propose a standard include file with default annotations
	Vassilios:	make sure that ALF sample libraries will be on the web
	Wolfgang:	communicate requested spec. corrections to Yatin
	Wolfgang:	invite Sente and Veritools for participation in power analysis
	all:		come up with modeling requirements for signal integrity