ALF meeting minutes 7/22 - 7/23 ********************************************************************************************** ALF DSM session 7/22/98 1:00PM - 6:00PM Attendees: Kevin Grotjohn LSI Logic Wolfgang Roethig NEC Tim Jennings Motorola Mike Andrews Mentor Graphics Sanjay Churiwala Cadworx Tim Ehrler VLSI Ted Vucurevich Cadence 1. Requirements for core modeling Kevin identified the following major requirements for IP modeling: - hierarchical representation of blocks and subblocks - parasitics with multiple fanout annotated to a pin of a block Ted added top-level routing requirement: - all interconnect at lower level must be visible Today's methodology uses hierarchical gate-level netlist mostly in VERILOG. Parasitics can be described in SPEF. Therefore there is no strong requirement to duplicate those description capabilities in ALF. The most important thing is to make a flow with OLA, SPEF, PDEF work, treating an IP block pragmatically as a design. New ALF definitions should be considered for added value. Added value items can only be identified by putting the flow into practice with existing capabilities. Therefore the industry needs to learn the use of OLA, SPEF flow first. LSI Logic's internal solution for this flow is scheduled for Q1 99. Cadence's strategy is to consolidate its internal solution first, and then build a bridge from TLF (Timing Library Format, also used for Power and Signal Integrity) to ALF and from CDE (Central Delay Engine) to OLA. 2. Parametrizeable cells Parametrizeable blocks can be modeled in ALF using TEMPLATES, but they are not visible in OLA. Only instantiations of templates with value definition for each parameter get translated into OLA. OLA and downstream tools do not see the parametrized template. Planning tools which explore implementations with different parameters need this information, as opposed to analysis tools which work on a design with fixed parameters. A simulation model generator for a parametrized cell must also see the parameter. VERILOG allows dynamically instantiated buses with parametrized buswidth. Currently OLA has no concept of parametrizeable cells. Making "buswidth" a predefined ALF keyword for 1.1 is the easy part. It may not even be required, because parameter names are free in VERILOG and probably in most other applications. The difficult part is to get the concept of parametrizeable cells into OLA which is evolving from the analysis-centric DPCM to a more general API. 3. Conditional arc existence Overloading the syntax for vector expressions by defining the first "?" as the delimiter between existence condition and the vector itself would not work, since a "?" could be used inside the existence condition itself. Tim Ehrler and Kevin brought up more items: iddq test condition, vector characterization condition, functional mode condition Wolfgang proposed to use predefined classes to accomodate all items in a general way. A general solution as opposed to a tool-centric solution is recommend, since different tools do different things with the same data. For example the IDDQ test tool from Mentor Graphics attempts to minimize static current by picking appropriate vectors, whereas other tools need to betold, which vector to use for IDDQ. 4. Review of vector modeling Due to the lack of time, the group was asked to review Wolfgang's document as a homework. Kevin requested waveforms for easier readability. Wolfgang's document contains also a section on pin-based power modeling recovered from an old ALF version. It was not included in the standard for the a similar reason as the DCL cookbook examples were not included in the IEEE 1481. 5. Signal integrity modeling Accurate modeling of analog operation constraints, such as limits for frequency, voltage, slewrate etc. constitute the main signal integrity requirements today. Wolfgang gave a proposal with an example that had to be changed after discussion. Convergence was achieved on the following extensionsfor ALF 1.1: - allow arithmetic models in lieu of annotations for max, min, typ - allow arithmetic models inside annotation containers limit, from, to - allow arithmetic model inside pins with the restriction not to reference other pins The signal integrity modeling requirement for piecewise-linear waveform of voltage or current versus time can be accomodated with ALF 1.0, as shown by another example from Wolfgang. The new keywords INDUCTANCE, NOISE_MARGIN, FLUENCE are probably needed to match TLF capabilities, but confirmation from Cadence is needed on this issue. ********************************************************************************** ALF spec review and planning session 7/23/98 9:00AM - 12:00 noon Attendees: Tim Ehrler VLSI Kevin Grotjohn LSI Logic Wolfgang Roethig NEC Mike Andrews Mentor Graphics Tim Jennings Motorola Sergei Sokolov Sente - by phone Yatin Trivedi Seva - by phone 1. Spec. Review Corrections for ALF 1.0.5 P 3-21. Section 3.4.8 Correct BNF for CELL definition: { ... } | ; instead of { ... | ; } P 3-22 Section 3.4.10 Correct BNF for PIN definition: same as for CELL definition P 3-31 Table 3-18 Description for keywords in INFORMATION missing P 3-44 Section 3.6.7.5 RISE and FALL changed from 'non-negative number' to 'number'. The paragraph above also needs to be corrected. P 4-20 Section 4.4.3 On line 5 of P 4-20 'voltage' should change to 'VOLTAGE' for cosmetic reasons. Changes proposed for ALF 1.0.6 P 3-23 Section 3.4.15 Tim Ehrler suggested that the definitions of header and header_item needed to change. The token 'identifier' needed to move from the header_item definition to the header definition. P 3-20 Section 3.4.6 Need a definition for class_object and class_objects in the 'Auxilliary Objects' section to allow for more than 'generic_objects' to be allowed within a class object. Specifically required are 'unnamed_assignments'. General comments on the document Kevin Grotjohn requests that there are semantic defintions added to explain the BNF definitions, to improve the readability of the BNF. Wolfgang suggests that the document should be reviewed to see which needed semantic definitons are missing, and also for the BNF to be optimised to remove unnecessary defintions (e.g. auxilliary objects that are only used once). Q:Are user-defined context-sensitive keyword possible? A: Yes (see 3.6). Parser should check syntax according to BNF and ignore semantics Items proposed for consideration for ALF 1.1 - Addition of FOOTPRINT - Multi-dimensional pins in STATETABLE - Addition of SWAP_CLASS as an alternative to 'FOOTPRINT' to define which cells may be swapped for each other; in conjunction with - RESTRICT_CLASS to limit the use of certain cells to certain applications that create or alter the design. Also required are standard names for known classes of application for use with this keyword - such as 'clock tree synthesis'. - Addition of existance vectors as discussed in previous afternoon. The issue of archival of ALF messages and the issue resolution process was discussed. A suggestion was made by Kevin Grotjohn to mimic the IR system used by the IEEE 1481 groups. Mike suggested that this should be done for changes from 1.0.x to 1.1. It was decided that a combined OLA/ALF IR system should be implemented. 2. Power & Timing modeling issues Sergei brought up the discussion item, whether a vector set for power should be complete, mutually exclusive, and whether default values should be provided and what should happen in case of overspecified vectors. Wolfgang: The ALF spec deliberately does not impose constraining requirements on vector sets, but provides means of describing any characterization vector set. Since the power analysis tools which drove the ALF spec in the past (POET, Quickpower) are no longer available, Sente has now the opportunity to be the driving force for power modeling and may chose to be proactive in ALF as well as in OLA. The issue of bus power modeling using `?!' operator and skew betweeen switching bits was also visited. Wolfgang pointed out that an example can be constructed. We settled on the following semantics for correlated timing constraints: - setup, hold in the same vector will be interpreted as setuphold. The pair of numbers will be found in the setup and hold model, respectively. - setup, hold, nochange in the same vector will be interpreted as nochange. The pair of numbers will be found in the setup and hold model, respectively. The nochange model requires no additional number. - setup, hold in different vectors will be interpreted as independent setup, hold constraints. Kevin requested that the waveforms from SDF spec to be used for ALF in order to back up the semantics. 3. ALF charter and roadmap Tentative positioning statement: While OLA is focussed on integrating libraries, tools and design flows, ALF is focussed on anticipating future modeling requirements. The ALF spec should be about 6-12 months ahead of the OLA spec. The group came up with the following draft for a roadmap: ALF 1.0 Nov. 97 ALF 1.1 Nov. 98 ALF 1.2 Nov. 99 Contents of ALF 1.1: - Parametrized cells for IP modeling - Cell characterization data for Signal Integrity - Timing abstraction data for Design Planning Target for ALF 1.2: - Signal integrity beyond cell characterization - Abstract physical library data for design planning, complementing existing standards - Concrete physical library data for backend, complementing existing standards ******************************************************************************************* Summary of New Action Items: ---------------------------- A.I Yatin will copy the VERILOG definition for ternary operator into the ALF spec. A.I. Tim will send email on header_item resolution to Yatin, Sanjay, ALF work group. A.I. Kevin will look for example where both independent AND correlated setup & hold are needed. A.I. Wolfgang will work out ALF description of NOCHANGE, SETUPHOLD A.I. Wolfgang will copy waveforms for timing constraint definition from SDF into ALF spec. A.I. ALF group will propose SIZE keyword for ALF1.0 A.I. (optional) Tim Ehrler will define a generalized ALF mux primitive using ALF behavioral language A.I. Tim Baldwin and Mike Andrews will attempt to confirm workability of current DFT modeling capabilities in ALF, especially for non-scan cells. A.I. Wolfgang will send Yatin relevant ALF mail for archival. A.I. Yatin will set up an IR based system on the website for OLA/ALF combined. A.I. ALF group will review Wolfgang's proposal for rigorous semantics of vector expressions in ALF. Wolfgang will add waveforms for ease of explanation. A.I. ALF group will get requirement for parametrized bus width in library to OLA group A.I. Wolfgang will develop a proposal for accomodating all types of conditions associated with vectors. A.I. Ted and Wolfgang will get Cadence information on new TLF keywords for signal integrity A.I. Tim Ehrler to provide Yatin with descriptions for keywords in INFORMATION container A.I. Yatin will review ALF spec. for missing semantic definitions of BNF terms. A.I. Mike will contact DPCM subgroup for starting harmonization of DPCM and ALF in OLA A.I. Wolfgang will construct ALF example with symbolic transition operator "?!" and SKEW for power modeling of a bus A.I. Wolfgang will provide BNF for generalized arithmetic model to Yatin Summary of Old Action Items: ---------------------------- A.I. Implementation of ALF state tables as a table of pin handles and Enumerations (John Beatty) - suspended A.I. Is it better for a synthesis tool to see a MUX (if-then-else) or AND/OR/NOT (Tim Baldwin) - done A.I. How to model dynamic logic in ALF (Kevin Grotjohn) - done A.I. What are the uses of footprint properties (Tim Baldwin) - done A.I. Investigate tool class properties (Kevin Grotjohn) - done A.I. Update to ALF spec for conditional existence vs. conditional value (ALF committee) - pending A.I. collect feedback on ALF signal integrity proposal (ALF committee) - done A.I. propose rigorous semantics for vector expressions in ALF (Wolfgang) - done A.I. collect requirements for core modeling in ALF (ALF committee) - done