ALF work Group meeting 8/27/98 (IBM - Burlington) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Next Meeting Time and Location ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Mentor (Portland) to host next meeting. ALF meeting will be held October 6 (Tue). OLA meeting to start October 7 (Wed) at 9am and to continue till October 8 (Thu) 5pm. Attendees ^^^^^^^^^ Ted Elkind Cadence Kolar Kodandapani Cadence Bob Dilly IBM Kevin Grotjohn LSI Logic Mike Andrews Mentor Graphics Archie Lachner Mentor Graphics Tim Jennings Motorola Wolfgang Roethig NEC Sergei Sokolov Sente Priti Vijayvargiya Synopsys Tim Ehrler VLSI Technology Old Action Items ^^^^^^^^^^^^^^^^ see OLA meeting minutes New Action Items ^^^^^^^^^^^^^^^^ provide non-proprietary information on IP modeling to Jay Abraham for the reflector - Ted Elkind, Ted Vucurevich publish roadmap for LEF standardization - Ted Elkind, Ted Vucurevich Modify ALF roadmap: replace "Concrete data for backend" by "detailed data for place&route" - Wolfgang Roethig Oversee compatibility management for DCL compiler versions - SI2 Testplan for OLAworx: unit test, regression test - Jay Abraham, Sanjay Churiwala Review ALF 1.0.5, chapter 3.9 - all Take a lead in proposing amendments for ALF 1.0.5, chapter 3.9 - Tim Ehrler Incorporate review changes into ALF 1.0.6 - Wolfgang, Yatin Trivedi Get IEEE 1164 source for 9-value logic - Ted Elkind Get definitions for timeskew and fullskew in SDF - Ted Elkind Change table 3-48 in ALF 1.0.5 from "wire" to "object" and provide semantics, if object is a cell, a block etc. - Wolfgang, Yatin Provide table for "@" (sequential if) and ":" (sequential elsif) operator in chapter 3.5 - Wolfgang, Yatin Find out whether literals in vector operator must be based in OLAworx, if at least one of them is a "?". - Tim Ehrler, Sanjay Review ALF modeling proposal for signal integrity w.r.t. TLF - Ted Vucurevich Find out the complete usage of "label" in SDF - Ted Elkind Remove prior art keywords for synthesis class explanation - Wolfgang Find less verbose syntax for connectivity in ALF - Wolfgang, Kevin Modify keywords and usage explanation for classes and conditions related to timing, test, characterization - Wolfgang Find out usage of aggregate concept beyond connectivity - Sergei Legalize reference to scalar pins inside arithemtic models inside bus pin in ALF spec. - Wolfgang, Yatin Input for macromodeling - all Draft for macromodeling - Wolfgang Agenda ^^^^^^ * general discussion For the interest of preserving the momentum from the OLA discussion, the agenda was changed to start with review of a memo from Cadence, which illustrated the issue of hierarchical timing modeling. This and more will be put on the reflector. We also spent some time for updating the synopsys representative on the OLA status, since Synopsys was not aware that the pertinent part of the OLA meeting was also open for their participation. Synopsys plans to support DCL timing and power by Q1 99, and is currently being supplied with OLA testcases as well. Version management and binary compatibility between 1481 DCL compiler and the new OLA compiler needs to be addressed by SI2. We are looking forward to a roadmap from Cadence on when and how LEF will fit in as a complementary standard to ALF and OLA. The ALF team expects that the detailed data for place & route will be supported in a standardized LEF complementary to ALF 1.2 in a Q4 1999 timeframe, and ALF will superseed TLF as a source for Cadence tools in the same timeframe. * vector modeling review minor corrections: P.4 alphabetic_bit_literal needs uppercase X P.5 change explanation for based_literal to make it more comprehensive P.7 insert "respectively" in line 6. major items: P.6 default behavior for unspecified functionality Group decided that no default behavior should be assumed unless explicitely specified by means of ALF language. A certain degree of freedom should reside in the simulation model generator (ALF2VERILOG, ALF2VITAL etc.) Chapter 3.9 in ALF 1.0.5 should be reviewed by all members with this regard. P.7 table for case comparison The standard behavior in case comparison versus logic comparison should be doublechecked with IEEE 1164. ALF attempts to be in harmonization with IEEE 1164 and also downstream compatible with both VERILOG and VITAL, which do not line up with IEEE 1164 to the same degree. P.8 Timing diagrams for each unary vector operator will be helpful. The group decided that the definition "?1" means either constant "1" or one single transition from anything to "1" should stand. Correlary, "??" means arbitrary constant or arbitrary single transition. A new symbol meaning arbitrary number of arbitrary transitions is needed as well. Suggestions were "?*", "?+". No limit of creativity. Review of sequel was postponed for next meeting. * timing modeling review findings from SDF: the "correlated timing constraints" in setuphold and recrem mean simply that the sum of setup & hold and recovery & removal must be non-negative. Additional constraint for simulation: if any value is negative, the sum of values must be greater than one simulation time unit. Generic ALF example for "retain" corresponding to SDF must be provided. Draft: VECTOR (?! addr -> 'b?'bx do -> 'bx'b? do) { RETAIN { FROM { PIN = addr; } TO { PIN = do; } // fill in header, table, equation or whatever } DELAY { FROM { PIN = addr; } TO { PIN = do; } // fill in header, table, equation or whatever } } The vector may or may not contain the transition to 'bx, this is up to the specification by the library provider. New timing constraints are being defined by SDF working comittee, for instance "fullskew" and "timeskew". The ALF group agreed to not simply duplicate new SDF keywords but to incorporate the definitions semantically into ALF using vector expressions for timing diagram description and the set of existing self-explaining keywords for arithmetic models. * power modeling review SKEW as definition of timing window in vector with simultaneously switching signals on a bus o.k. for Sente. Power as a function of SKEW as shown in example also o.k. RESISTANCE has multiple meanings for power. Driver resistance should be inside RISE or FALL container, state-dependent driver resistance should be inside vector, as shown in ALF 1.0.5 chapter 4.13.2. Pullup and pulldown resistors should use be inside pin with annotations PULL=up and PULL=down, respectively. Resistance of input pin without further annotation is parasitic wire resistance of the pin inside the cell. * new arithmetic models Add EARLY, LATE as annotation_containers, allow RISE, FALL to be annotation_containers in the same way as MIN, TYP, MAX, and allow annotation_containers to contain full arithmetic models. INDUCTANCE, NOISE_MARGIN, FLUENCE as new arithmetic models need endorsement from Cadence in order to be accepted. * predefined classes for synthesis Kevin's proposal is accepted by ALF work group. Minor modification: remove prior art keywords from semantic explanation. Modified proposal will be presented to OLA group at next meeting. OLA group needs to decide downstream usage of the predefined classes. * predefined classes for modes and conditions Wolfgang's proposal is accepted with the following modification. TEST_CONDITION, TEST_VECTOR is to be changed to CHARACTERIZATION_CONDITION, CHARACTERIZATION_VECTOR and will be used by characterization tool only. Tester tool will use the VECTOR and eventual EXISTENCE_CONDITION directly, i.e. TEST_CONDITION, TEST_VECTOR would be redundant. A TEST_CLASS keyword for annotation will be added. The annotation value may be "iddq" etc. * Connectivity Needed in ALF for stitching distributed RC networks together, when logical and physical pins are not identical and internal nodes are present. Syntax of current proposal is too verbose and needs to be made more compact (SPEF-like). Sergei brought up the concept of "aggregate" as opposed to "group". The team concluded that the aggregate concept for connectivity can be emulated in ALF today by defining virtual buses. Only if the aggregate concept has applications beyond connectivity, we need to think about it. Tim brought up the issue of pin capacitance on individual pins of a bus. The proposed solution looks as follows, which needs to be legalized in ALF: PIN[1:3] my_bus { CAPACITANCE c1 { PIN = my_bus[1]; // fill in header, table, equation or whatever } CAPACITANCE c2 { PIN = my_bus[2]; // fill in header, table, equation or whatever } CAPACITANCE c3 { PIN = my_bus[3]; // fill in header, table, equation or whatever } } * Macromodeling Parametrized cores could be modeled with templates, but new semantics are needed to distinguish between "statically" instantiated templates where each placeholder gets a fixed value and "dynamically" instantiated templates, where each placeholder is a free parameter. Tim requested to use a different keyword than TEMPLATE in order to make the distinction clear. Wolfgang suggested to use the same keyword and put the distinction into the instantiation, since the same core could be instantiated dynamically (during design planning) and statically (as a hardcore in physical design). Kevin requested that design parameters should be allowed as arithmetic models. ALF group will draft a proposal for the next meeting and present the concept to the subsequent OLA meeting. * Conclusion All agenda items were visited, yet not exactly in the order outlined in the agenda. We also attempted to close some OLA issues. Thanks to everybody for valuable contributions. Corrections and comments to the meeting minutes are welcome.