ALF conference call, Jan.18 10:30AM - 12:00 noon Mike Andrews Mentor Graphics Darshan Rauniyar Mentor Graphics Sergei Sokolov Sente Tim Ehrler VLSI Technology Arun Balakrishnan NEC Wolfgang Roethig NEC Agenda: * finish review of ALF 1.0.8, chapter 4 4.9.4 new chapter for pin reference inside bus Consensus was reached that annotations or arithmetic models in the scope of a bus should apply to the total bus, not to each individual pin. Annotations or arithmetic models applying to individual bits of the bus should be put into the scope of individual scalar pins, as shown. A.I. Add text to the normative section, chapter 3.6.10 for this issue -- Wolfgang DONE 4.15.2 and 4.15.3 are o.k. * revisit items from chapter 3 for more detailed review and corrections 2.2.3 Verilog model revisited by Sergei, clarifications from Ted, Wolfgang, Kevin (by email) Purpose of ALF is source for simulation model in LIBRARY as opposed to model inference for synthesis in DESIGN A.I. add explanation in text, change title of figure 2-2, 2-3 into "Simulation model of a flipflop .." -- Wolfgang DONE A.I. cosmetic correction to table 3-4, chapter 3.4.17, suggested by Tim Ehrler: when plural occurs in BNF item, put plural also consistently in explanation -- Wolfgang DONE A.I. corrections suggested by Sergei Sokolov: 3.5.4, in description of the * literal in Table 3-16, suggest "a number or arbitrary signal transitions, including ..., with the initial value ..." for all rows p. 57, at the very top - quadruple is misspelled -- Wolfgang DONE 3.9.2 and 3.9.3 revisited by Tim Ehrler - o.k. 3.9.4 revisited by Tim Ehrler: eventually acceptable, but would still like to have initial_value as pin annotation. Wolfgang's suggestion: This is part of features to drive a simulation model, the complete set of features necessary for simulation model should be discussed in face-to-face meeting. A.I. put simulation model issues on agenda for meeting Febr. 9 -- Wolfgang * discuss completeness of features for ALF 1.1 and decide spec. freeze. Wolfgang's proposal: spec. should be frozen by nextALF meeting Febr. 9 and approved by the time of the HLD conference April 6-9, which is sponsored by OVI and VIUF. Time frame looks o.k. to everybody Feature set in ALF 1.0.8 is currently proposed feature set for ALF 1.1. Some of the features (e.g. multi-level hierarchical function description) will not be immediately supported by OLA. A.I. Sente has concrete plans for support of ALF and OLA. Sergei will contact Jay for spec. of available OLAworx features Feature "dynamic template instantiation" will be included in ALF 1.1 as means for support of parametrizeable cores, although OLA support is not immediately available. A.I. Include dynamic template proposal in spec. -- Wolfgang A.I. Develop corresponding OLA model -- OLA work group Feature "parasitic modeling within cores" will not be included in ALF 1.1, since it has not been reviewed extensively enough. It will be on the agenda for ALF 1.2. OLA will use SPEF methodology short-term. The ALF spec. will allow arithmetic models for parasitics as opposed to backannotated numbers long-term. Wolfgang proposed to start IEEE standardization by the time when ALF 1.1 gets OVI approval. Realistically, it will take 2 to 3 years to get an IEEE standard ready. Modifications to the spec. are allowed until final ballot. The intent is to generate momentum from which OLA also will benefit. Eventually the ALF/OLA cross-reference will be part of the same IEEE standard. Details will be discussed in the face-to-face meeting. Guidelines for IEEE standard development can be found on IEEE webpage. A.I. write roadmap for IEEE standardization and present it Febr. 9 to ALF and OLA work groups -- Wolfgang Arun suggested also to contact VHDL international for additional endorsement. A.I. find interested people from VHDL international -- all A.I. Contact Vassilios for further discussion on ALF roadmap -- Wolfgang ALF 1.0.8 has been staged on www.eda.org/alf by Mike Andrews. ALF 1.0.9 will be staged prior to the meeting Febr. 9.