Library harmonization meeting Feb 23 2004 from 9AM to 12noon at Artisan, Sunnyvale Attendees --------- John Williams, Markanix Maddu Karutanate, V-cube Hemant Joshi, Artisan Andrea Cosmin, Artisan Kevin Kranen, Synopsys Wolfgang Roethig, NEC Dave Allen, Sequence (phone) Robert Jones, Magma (phone) Maulik Dave, self (phone) Next meeting ------------ March 22, 9AM to 12noon, hosted by Cadence, San Jose Action item and update ---------------------- Write a proposal for ontology, suitable as a chapter in DoD Owner: Alex Zamfirescu WIP Write short proposal for generic libraries Owner: Alex Zamfirescu OPEN Make list of liberty items for which ALF representation is unknown Owner: Fereshteh/Kevin WIP Main areas: power, flow-specific representation Kevin: Rajesh has a partial list, Kevin will send it out by March 1 Write short elaboration on requirements noise items (see DoD section 2.4) Owner: Matt Liberty WIP - Cadence discussions ongoing Write paragraph about rules for libray data usage model by application for possible inclusion in scope Owner: Alex OPEN Investigate *_capacitance semantics Owner: Kevin Kranen OPEN Found the following capacitance-related keywords in liberty doc: capacitance default_wire_load_capacitance fall_capacitance rise_capacitance max_capacitance min_capacitance fanout_capacitance total_output_net_capacitance equal_or_opposite_output_net_capacitance total_output1_net_capacitance total_output2_net_capacitance related_out_total_output_net_capacitance related_out_total_output_wire_capacitance reference_capacitance default_capacitance Investigate relevance for intrinsic_* Owner: Kevin Kranen OPEN Kevin: Any keywords rerated to the linear or CMOS2 delay calculation model can be considered not relevant. However, the intrinsic_* keywords seem to be still relevant for non_seq_setup and skew constraint. Kevin to investigate. Names for obsolete delay models are: - generic_cmos (that's linear) - cmos2 - piecewise_cmos Names for relevant delay models are: - table_lookup - polynomial Related AI: Find timing keyword for skew constraint, since intrinsic_* seems to be obsolete Owner: Wolfgang see Kevin's related AI Note: figure 10-17 in liberty doc missing Give feedback on conditional timing doc and examples Owner: Greg Hackney OPEN - Wolfgang solicited feedback from others as well. Show a timing model involving a bus in liberty Owner: Hemant WIP Example shows: 1 bit to many bits: clk to Q 1 bit to 1 bit: TQ to Q many bits to many bits: need maybe multiple times 1 bit to many bits? Hemant will follow up Show a timing model involving a bus in ALF Owner: Wolfgang WIP Wolfgang will combine his example with Hemant's example. Optional item: John will investigate, whether there is any real library application that needs 3 groups (many to many to many). Find out whether timing_sense is applicable to setup, hold Owner: Hemant DONE Hemant showed example where timing_sense is not needed. Table 4, 5, 6, 7, 9: put "not applicable" for timing_sense. Library compiler seems to ignore timing_sense in these cases. Experiment with library compiler how to describe constraints between async. preset and clear Owner: Hemant WIP - by next meeting Question to Synopsys: Are there plans to support pulsewidth, period as table or polynom instead of scalar attribute in the future? Owner: Kevin WIP - provide answer by March 1 Put timing diagrams into section 1.1 Owner: Wolfgang DONE Put slew_derate_from_library into section 1.2 Owner: Wolfgang DONE Question: Is timing sense applicable for rising_edge, falling_edge? Owner: Kevin NEW Update the timing doc as follows: Table 2: timing sense applicable for three_state_enable Table 3: put Timing_type "combinational" for retaining_* in table Timing_sense is o.k. Owner: Wolfgang NEW Sec. 1.11: Is min_period or minimum_period the correct keyword? Both appear in liberty doc. Owner: Kevin NEW Update 1.12 as follows: Which thresholds apply (input or output) for setup and hold? Should be input. Add "Per default" into the 2nd paragraph. Mention restriction for slew_upper_threshold_rise - slew_lower_threshold_rise must be equal to slew_upper_threshold_fall - slew_lower_threshold_fall Mention the purpose of slew thresholds: because of non-linear waveform and waveform degradation accross interconnect. Owner: wolfgang NEW Update Table 11 as follows: ABSOLUTE, INCREMENT: not applicable PATHPULSE, PATHPULSEPERCENT: not applicable COND, CONDELSE: see sec. 1 12 SCOND, CCOND: see following paragraph LABEL: TBD PORT: not applicable INTERCONNECT: related to thresholds (see 1.11) and capacitance descriptions (see other AI) NETDELAY: not applicable DEVICE: not applicable BIDIRECTSKEW: see 1.9 Owner: wolfgang NEW Investigate propagation delay concept (rise_transition, fall_transition). Give example in ALF. Owner: Wolfgang NEW Power discussion ---------------- Which are the important items? Kevin: accounting system in liberty leakage power, internal power (also glitching power), switching power John: energy storage for functional integrity, e.g. refresh requirement for dynamic logic, immunity against noise, e.g. cosmic rays, rate of energy loss by leakage. Fundamental idea is to use energy as a primary variable in cell modeling. Define integrity in terms of signal energy versus noise energy. Karu: define the accounting system, then the lib2alf xref Dave: accounting system multiple power supplies Andrea: leakage power More thoughts on leakage power: - substrate models for accurate leakage power - state-dependency - introduce substrate port of the transistor - leakage variation subject to process statistics System-level power: power dependent on instructions executed by a microprocessor possible approach: use abstracted ALF vector concept RF design: e.g. S-parameters for transient voltage drop energy loss due to RF effects, depends on layout of a trace