Library harmonization meeting March 22 2004 from 9AM to 12noon at Cadence, San Jose Attendees --------- John Williams, Markanix Andrea Cosmin, Artisan (phone) Bhuwnesh Pandey, Cadence (phone) Koorosh Nazifi, Cadence Alex Zamfirescu, ASC Kevin Kranen, Synopsys Wolfgang Roethig, NEC Next meeting ------------ April 26 at Synopsys Action item and update ---------------------- Write a proposal for ontology, suitable as a chapter in DoD Owner: Alex Zamfirescu WIP - please send email with powerpoint presentation Write short proposal for generic libraries Owner: Alex Zamfirescu WIP - will send by March 31 Make list of liberty items for which ALF representation is unknown Owner: Fereshteh/Kevin WIP Main areas: power, flow-specific representation Kevin: Rajesh has a partial list, Kevin will send it out by March 1 Kevin reminded Rajesh, please send as early as possible Write short elaboration on requirements noise items (see DoD section 2.4) Owner: Matt Liberty WIP - Cadence discussions ongoing Reassigned to Bhuwnesh/Koorosh Write paragraph about rules for libray data usage model by application for possible inclusion in scope Owner: Alex Zamfirescu WIP - will send by March 27 Investigate *_capacitance semantics Owner: Kevin Kranen Found the following capacitance-related keywords in liberty doc: capacitance default_wire_load_capacitance fall_capacitance rise_capacitance max_capacitance min_capacitance fanout_capacitance total_output_net_capacitance equal_or_opposite_output_net_capacitance total_output1_net_capacitance total_output2_net_capacitance related_out_total_output_net_capacitance related_out_total_output_wire_capacitance reference_capacitance default_capacitance DONE - see Kevin's email Investigate relevance for intrinsic_* Owner: Kevin Kranen Kevin: Any keywords rerated to the linear or CMOS2 delay calculation model can be considered not relevant. However, the intrinsic_* keywords seem to be still relevant for non_seq_setup and skew constraint. Kevin to investigate. Names for obsolete delay models are: - generic_cmos (that's linear) - cmos2 - piecewise_cmos Names for relevant delay models are: - table_lookup - polynomial DONE - see Kevin's email Related AI: Find timing keyword for skew constraint, since intrinsic_* seems to be obsolete Owner: Wolfgang DONE - see updated doc Corrections to liberty doc: Figure 10-17 in liberty doc missing and others Owner: Kevin WIP - will be in next release (April) Give feedback on conditional timing doc and examples Owner: Greg Hackney DONE - see Greg's email Show a timing model involving a bus in liberty Owner: Hemant WIP Example shows: 1 bit to many bits: clk to Q 1 bit to 1 bit: TQ to Q many bits to many bits: need maybe multiple times 1 bit to many bits? Hemant will follow up Show a timing model involving a bus in ALF Owner: Wolfgang WIP Wolfgang will combine his example with Hemant's example. Optional item: John will investigate, whether there is any real library application that needs 3 groups (many to many to many). DONE Experiment with library compiler how to describe constraints between async. preset and clear Owner: Hemant WIP - by next meeting Question to Synopsys: Are there plans to support pulsewidth, period as table or polynom instead of scalar attribute in the future? Owner: Kevin DONE - see Kevin's email Question: Is timing sense applicable for rising_edge, falling_edge? Owner: Kevin DONE - answer is no Update the timing doc as follows: Table 2: timing sense applicable for three_state_enable Table 3: put Timing_type "combinational" for retaining_* in table Timing_sense is o.k. Owner: Wolfgang DONE - see updated doc Sec. 1.11: Is min_period or minimum_period the correct keyword? Both appear in liberty doc. Owner: Kevin DONE - see Kevin's email Update 1.12 as follows: Which thresholds apply (input or output) for setup and hold? Should be input. Add "Per default" into the 2nd paragraph. Mention restriction for slew_upper_threshold_rise - slew_lower_threshold_rise must be equal to slew_upper_threshold_fall - slew_lower_threshold_fall Mention the purpose of slew thresholds: because of non-linear waveform and waveform degradation accross interconnect. Owner: wolfgang DONE - see updated doc Update Table 11 as follows: ABSOLUTE, INCREMENT: not applicable PATHPULSE, PATHPULSEPERCENT: not applicable COND, CONDELSE: see sec. 1 12 SCOND, CCOND: see following paragraph LABEL: TBD PORT: not applicable INTERCONNECT: related to thresholds (see 1.11) and capacitance descriptions (see other AI) NETDELAY: not applicable DEVICE: not applicable BIDIRECTSKEW: see 1.9 Owner: wolfgang DONE - see updated doc Investigate propagation delay concept (rise_transition, fall_transition). Give example in ALF. Owner: Wolfgang NEW Look for rise_propagation, fall_propagation keywords in liberty spec Power discussion ---------------- State-dependent and state-independent leakage power in liberty: usage is mutually exclusive (corresponds to MEASUREMENT=ABSOLUTE in ALF). Table or polynomial models for leakage power supported, but not yet documented. Alex: Do we need abstractions of state? Do we need power-specific state-machines? Which accounting method is more suitable for instantaneous power: supply oriented or dissipation oriented? Thermal analysis support: do we need another item in the DoD? Which rank should it have? Transient energy: measured over a large-enough time window Power calculation always assumes that the observed time window is equal or larger than the measurement time window for energy characterization. For power arc in liberty: Not possible to specify related pin switching direction, must use state-dependent arc to capture this scenario. To do: power with no related pin. To do: power with more than one related pin. What happens if the transitions on multiple related pins happen simultaneously? Answer: no double count, because output pin just switches once. Proposed discussion items on power for next meeting: switching activity, simultaneous switching, data-dependency Timing discussion ----------------- State-dependent timing: "default" is used when none of the "when" conditions evaluates true. SDF: CONDELSE is not applicable INTERCONNECT: no corresponding library statement, but the library influences the outcome of the interconnect delay calculation by virtue of Threshold, net capacitance definitions in the library. LABEL: Possible the name of the timing group gets translated into an SDF label? many-to-many mappings for bus timing: reviewed John Williams' doc. New action items ---------------- Is state-independent leakage power value the default, if no state matches? Owner: Kevin NEW Follow-up on missing documenation on table/polynomial modeling style for leakage power Owner: Kevin NEW Call for vote on thermal analayis over email Owner: Wolfgang NEW Capitalize "Liberty" in doc, add "TM" at first occurence. Owner: Wolfgang NEW Update power doc as per discussion Owner: Wolfgang NEW Update timing doc as per discussion Owner: Wolfgang NEW Is the functional equivalence in the equal_or_opposite_output rule enforced, or can the model with 2 output capacitances also be used for any cell with 2 outputs ,given an arc-specific condition? What about applicability for timing? Example: cells with functionally correlated outputs, but not strictly equivalent or complementary. Owner: Kevin NEW Need clarification on rising|falling|switching_together semantics. See Liberty doc, page 9-40 This also leads to an abstraction methodology. Owner: Kevin NEW Find out whether more than 2 voltages are supported: voltage2, voltage3 etc. Owner: Kevin NEW Prepare kick-off material about switching activity, causality for power eval Owner: Alex NEW