Library harmonization meeting June 18 2004
from 9:30AM to 12:30PM at NEC, Santa Clara

Attendees
---------
John Williams, Markanix
Andrea Cosmin, Artisan (phone)
Hemant Joshi, Artisan (phone)
Koorosh Nazifi, Cadence (phone)
Kevin Kranen, Synopsys
Maddu Karunaratne, V-cube
Dan Holt, V-cube
Wolfgang Roethig, NEC

Action item status
------------------

Write short proposal for generic libraries
Owner: Alex Zamfirescu
WIP - will send by begin of June
no update

Make list of liberty items for which ALF representation is unknown
Owner: Fereshteh/Kevin
WIP
Main areas: power, flow-specific representation
Kevin: Rajesh has a partial list, Kevin will send it out by May 7.
Kevin reminded Rajesh, please send as early as possible.
Will get it done before next meeting (July 12)

Write short elaboration on requirements noise items (see DoD section 2.4)
Owner: Matt Liberty
WIP - Cadence discussions ongoing
Reassigned to Bhuwnesh/Koorosh, Koorosh will give update by May 7.
Will get update by June 25

Write paragraph about rules for libray data usage model by application
for possible inclusion in scope
Owner: Alex Zamfirescu
WIP - will prepare discussion material for next meeting in June
no update

Corrections to liberty doc: Figure 10-17 in liberty doc missing and others
Owner: Kevin
WIP - will be in next release (April). Kevin to confirm availability of new release.
DONE - figure is in version 2003.12  (and hopefully all versions thereafter)

Investigate propagation delay concept (rise_transition, fall_transition).
Give example in ALF.
Owner: Wolfgang
OPEN
Look for rise_propagation, fall_propagation keywords in liberty spec
Wolfgang looked for semantic description or example in liberty doc 2003.10,
but could not find.
Kevin sent a doc with description to Wolfgang.

Follow-up on missing documentation on table/polynomial modeling style for leakage power
Owner: Kevin
Table not supported, polynomial supported with voltage and temperature as dimensions.
DONE - documented in 2003.12

Capitalize "Liberty" in doc, add "TM" at first occurence.
Owner: Wolfgang
DONE - see latest version of DoD

Is the functional equivalence in the equal_or_opposite_output rule enforced,
or can the model with 2 output capacitances also be used for any cell with
2 outputs, given an arc-specific condition? What about applicability for timing?
Example: cells with functionally correlated outputs, but not strictly
equivalent or complementary.
Owner: Kevin
WIP
For timing, the keyword is related_output.
Need to know whether equal_or_opposite_output is supported for full adder.
Co-owner: Hemant

Need clarification on rising|falling|switching_together semantics.
See Liberty doc, page 9-40
This also leads to an abstraction methodology.
Owner: Kevin
WIP
rising|falling|switching_together means that power is associated with a group of pins
that rise|fall|switch together in a specified time interval.
The parent pin is not part of the group of pins.
What is the position of the switching interval relative to the event on the parent pin?

Prepare kick-off material about switching activity, causality for power eval
Owner: Alex
WIP - discussing in the meeting
Glitch power, i.e. multiple switching inputs causing no or incomplete output switch
is a special case.
Liberty: use internal_power construct, possible with "when" statement.
Power can be function of slew, load, but not of the width of the glitch.
ALF: use vector expression that describes the glitch event.
Power can be function of the width of the glitch.

Test which modeling style works for bus pins:
When is it necessary to define scalar pins within bus?
Is name match between bus and scalar pin within bus mandatory?
If scalar pin not declared, can still refer to bits of bus individually?
Owner: Hemant
OPEN
will clarify by 6/24

Clarify usage model of bundle and bus:
Only supported in power or also in timing?
Are all the power relationships with bus/bundle etc. supported in timing?
Is the "related_bus_pins" keyword supported for timing?
Owner: Kevin
OPEN
Co-owner: Hemant
Hemant will send example for setup between clock and address of memory
SDF file will have bit-blasted timing arcs.

Update DoD: correct "electromigration" to "reliability",
put thermal analysis
Owner: Wolfgang
DONE

Find the chapter in IEEE 1497 about the semantics of LABEL
Possible the name of the timing group gets translated into an SDF label?
Still open, need SDF 1497 doc to find the LABEL semantics in SDF.
Owner: Alex
OPEN
Reassigned to Dan Holt

Investigate the best editor for ontology to be used by this group.
Come up with basic ontology encompassing cell, pin and timing arc
Owner: John, Alex
WIP
Looking at WOL (Web Ontology Language) in context of Protege framework. 
Will publish example with timing arc by June 30.

Find out Artisan's definition of static power versus leakage power
Owner: Andrea
DONE
Artisan's definition of static power: input pin switches, but output pin does not.
We should use the terminology "internal_power" on input pin.

Next meeting
------------
Main topic:
Types, attributes, basic structure of a library model.
Will mesh nicely with ontology.

Date: July 12
Tentative host: Mentor Graphics