Library harmonization meeting August 23 2004 at Mentor Graphics, San Jose Attendees --------- Dennis Brophy Mentor John Williams Markanix Wolfgang Roethig NEC Maulik Dave self (phone) Koorosh Nazifi Cadence (phone) Action item status ------------------ Make list of liberty items for which ALF representation is unknown Owner: Fereshteh/Kevin WIP Main areas: power, flow-specific representation Kevin: Rajesh has a partial list, Kevin will send it out by May 7. Kevin reminded Rajesh, please send as early as possible. Will get it done before next meeting (July 12) (hopefully) WIP Write short elaboration on requirements noise items (see DoD section 2.4) Owner: Matt Liberty WIP - Cadence discussions ongoing Reassigned to Bhuwnesh/Koorosh, Koorosh will give update by May 7. Will get update by June 25 WIP Cadence committed to report their requirements in August 2004 meeting WIP Investigate propagation delay concept (rise_transition, fall_transition). Give example in ALF. Owner: Wolfgang OPEN Look for rise_propagation, fall_propagation keywords in liberty spec Wolfgang looked for semantic description or example in liberty doc 2003.10, but could not find. Kevin sent a doc with description to Wolfgang. WIP Wolfgang is reviewing the doc Is the functional equivalence in the equal_or_opposite_output rule enforced, or can the model with 2 output capacitances also be used for any cell with 2 outputs, given an arc-specific condition? What about applicability for timing? Example: cells with functionally correlated outputs, but not strictly equivalent or complementary. Owner: Kevin For timing, the keyword is related_output. Need to know whether equal_or_opposite_output is supported for full adder. Co-owner: Hemant WIP New action items ---------------- Document glitch and switching activity modeling in ALF Owner: Wolfgang WIP discussing in this meting Discuss and document SDF LABEL usage Owner: Wolfgang (all) WIP discussing in this meeting Provide dont_use, dont_touch, dont_fault doc to working group Reason: dont_use, dont_touch, dont_fault not documented in liberty doc Need Synopsys tool document, which is not available for everybody Owner: Kevin Kranen WIP Wolfgang got document from Synopsys, reviewing Raise ordinality support issue on OWL reflector Owner: John DONE John got feedback from the protege reflector. Ordinality currently not supported. Recommendation: table the ontology work until ordinality or an equivalent way for quantification will be available. Describe how SDF label applies to Liberty and ALF. Owner: Wolfgang VOID duplicates previous item scan_group not described in liberty doc. Find other doc for work group. Owner: Kevin OPEN Describe example for clock-gating cell Owner: Hemant OPEN Question: which application tool will use the statetable? Why not use the "latch" statement? Next meeting ------------ Mon Sep 27, 9:30 - 12:30 at Cadence Technical discussion ==================== Glitch and activity propagation ------------------------------- A) How switching activity propagates through logic circuit B) what is the definition of a glitch C) How can switching activity propagation be applied in the presence of glitch A) How switching activity propagates through logic circuit John: need to harmonize with SDF. Dennis: Verilog and VHDL also have glitch modeling concepts. Wolfgang: VHDL support arc-specific glitch propagation, Verilog supports only global. B) what is the definition of a glitch 1) "Power" centric view a) logic gate toggles unnecessarily during one clock cycle, events are never recorded in storage element, this results in unnecessary power consumption, or b) input(s) of logic gates toggle(s) too fast to be noticed on the output, i.e., output does not change state or changes state only partially, depending on the timing of the input events, this still results in unnecessary power consumption 2) "Signal Integrity" centric view noisy signal that is in an erroneous state while being recorded in a storage element, noise is caused by a) capacitive coupling (xtalk) or b) inductive coupling (specially mutual inductance) or c) voltage drop Glitch definition according to VITAL IEEE1076.4-2000, section 9.3, 1st paragraph: "A glitch occurs when a new transaction is scheduled at an absolute time which is greater than the absolute time of a previously scheduled pending event which results in a preemptive behavior." Group suggests to adopt a definition for "glitch" that is compatible with this baseline definition. Proposed terminology: 1) a) unnecessary switching 1) b) glitch 2) a) noise caused by capacitive crosstalk 2) b) noise caused by inductive coupling 2) c) noise caused by supply voltage fluctuation SDF label usage --------------- In SDF, label applies to a single specparam found in Verilog. In Liberty and ALF, label applies to each model found in a timing group and a vector, respectively. 1-to-1 mapping between a library (either liberty or ALF) and SDF can only be accomplished, if a timing group or a vector contains a single model, corresponding to a specparam in Verilog. Alternative solution in ALF: A model can also have a name, and that name can be the same as a specparam in Verilog. But this solution does not apply to liberty. Need to find out how liberty-SDF xref for labels is currently done.