Design Constraints Overview

Purpose of Design Constraints

Describe restrictions on the usage of a VC within a system chip design, or on the implementation of the VC itself.

Interface constraints describe requirements for the interfaces to the VC. Interface constraints apply to the system chip design surrounding the VC, and they ensure that the VC will work properly in the system chip context. Interface constraints are required for soft, firm, and hard VCs.

Internal constraints describe requirements for the internal implementation of the VC. They apply to the VC itself, and they are used for soft and firm VCs to ensure that the VC implementation (which is done by the VC integrator) meets the specifications for the VC. A VC will generally contain hierarchy, and internal constraints may be used to describe requirements for lower levels of hierarchy within the VC, as well as requirements for the VC as a whole.

Types of Constraints Required

Timing Constraints

Timing constraints are related to the basic delay model in the sense that the timing constraints describe what needs to be implemented, while the basic delay model describes what has already been implemented (or at least estimated).

Detailed interface timing constraints on non-clock signals are usually included in the basic delay model.

• Interface Constraints
  • Setup, hold, removal, recovery, pulse width, nochange
• Internal Constraints
  • Arrival times at inputs
  • Required times at outputs
  • Internal and external combinational delay (for purely combinational paths)
  • Multi-cycle paths
  • False paths
  • Data signal transition times
  • Transparent latch borrowing limits

Clock Constraints

Clock constraints describe requirements for the clock signals provided to the VC, and (for soft and firm VCs) the required implementation of the clock distribution network within the VC.

• Interface Constraints
  • Clock frequency
  • Duty cycle
  • Jitter
  • Relationship between multiple clocks provided to the VC
• Internal Constraints
  • Insertion delay
  • Skew
  • Transition times
  • Pulse width
  • Gating
  • Type of distribution to be used and restrictions on its structure (i.e., tree vs. trunk, how many levels, what kind of buffers and routing style).
  • Generated clock waveforms

Logic Architecture Constraints

Logic architecture constraints describe the designer's intent for aspects of the logical implementation of the design which cannot be expressed directly in the RTL description.

Logic architecture constraints only apply to soft VCs, and there are only internal constraints.

• Internal Constraints
  • Hierarchy manipulations (flattening or preserving sections of the logical hierarchy),
  • State machine encoding
  • Resource sharing restrictions
  • Mapping/binding restrictions for certain operators or design objects.

Area Constraints

Area constraints describe requirements for how much area may be consumed by a portion of the design. For synthesis, the constraints may describe just the area consumed by the primitives themselves, while in floorplanning and place and route the constraints may account for various types of physical overhead such as power and clock distribution.

Area constraints only apply to soft and firm VCs, and there are only internal constraints.

• Internal Constraints
  • Primitive area
  • Power distribution area
  • Clock distribution area
  • Test logic area

Physical Implementation Constraints

Physical implementation constraints describe requirements for the topology and routing of the internals of a firm VC.

• Internal Constraints
  • Regions
  • Placement groups
  • Datapath topology
  • Wide wire specifications
  • Power distribution structures

Power Constraints

Power constraints describe requirements for the power consumption of a VC.

• Interface Constraints
  • Current requirements for power pins
• Internal Constraints
  • Average, peak dynamic power
  • Static power
  • Leakage power
  • Specified for the VC as a whole, for hierarchical blocks within the VC, or for particular signals within the VC.

Test Constraints

Test constraints describe requirements for the test logic within a soft or firm VC. These constraints are used in inserting the test logic and verifying that the test logic functions correctly.

• Interface Constraints
  • Type of test socket provided
  • Test clock waveforms
  • Other constraints to be defined by the Test DWG
• Internal Constraints
  • Type of test structure to be inserted
  • Scan chain ordering
  • Test coverage
  • Other constraints to be defined by the Test DWG

Environmental/Operating Conditions

Environment/operating conditions describe the range of operating conditions over which the VC is expected to function properly. A Hard VC may have tighter restrictions than the underlying technology.

• Interface Constraints
  • Process, voltage, and temperature ranges
  • Required driver strengths
  • Required driver types
  • Input slew rates
  • External capacitance
• Internal Constraints
  • Driver strength
  • Driver type
  • Input slew rate
  • External capacitance