Re: DC-WG: 6/9 meeting minutes

Mark Hahn (mhahn@cadence.com)
Tue, 23 Jun 1998 07:28:42 -0700

On Jun 22, 4:38pm, Steve Grout wrote:
> Subject: DC-WG: 6/9 meeting minutes
>
> Mark -
>
> > 5. Steve 6/22 First draft of taxonomy for parasitics
> > boundary conditions
> > ...
>
> Mark - please give me a sanity check on this. I am interpreting the
> above, per our brief conversation at SLDL, that my scope initially
> includes all definitions about parasitics with respect to timing,
> e.g.,
>
> ...
> - pin capacitance to substrate
> - pin drive
> - pin loading
> - netsegment lumped capacitance to substrate
> - netsegment lumped capacitance to some other netsegment
> - netsegment per unit capacitance to substrate
> - netsegment lumped serial resistance
> - netsegment per-unit serial resistance
> - netsegment lumped self-inductance
> - netsegment per-unit self-inductance
> - netsegment lumped mutual-inductance to some other netsegment
> - netsegment per-unit self-inductance resistance to some other netsegment
> - power supply drive effective impedance
> - ground/substrate effective impedance
> - substrate thermal impedance
> - substrate per-unit-area thermal impedance
> ...

I think that most of these are technology parameters which would
be specified by the foundry as part of the library, rather than
constraints/operating environment conditions which are specified
by the user. I was expecting the parasitics boundary conditions
to include
- external load (lumped capacitance)
- could be separated into pin capacitance and wire capacitance
- external fanout (# pins, wire load model name)
- external detailed parastics (SPEF or DSPF file)
- this is not widely supported today, but I believe it will
become essential for hierarchical physical design
- driver cell type
- drive strength
- input slew

> with the definitions applicable to today's ASIC practices as well
> as the coming VDSM (250nm and below down to 100nm) RLCM distributed
> parasitics etc.

We should definitely address things down to 100nm, or the standard will
be obsolete before it's released.

Mark

-- 
Mark Hahn                                          phone: (408) 428-5399
Architect, Deep Submicron Business Unit            fax:   (408) 428-5959
Cadence Design Systems                             email: mhahn@cadence.com