Attendees:
Mark Hahn, Cadence (Chair)
Jin-sheng Shyr, Toshiba (Co-chair)
Tom Dewey, Mentor
Steve Grouts, Sematech
Dan Moritz, LSI Logic
David Pefourque, Fujitsu
Greg Schulte, Ambit
Jim Swift, IBM
Next Meeting:
The next meeting will be a teleconference on Tuesday, 7/21/98,
from 9-11 am PDT.
New action items:
Who When What
---------- ------ --------
1. Mark 7/21 Get Enrico to send Powerpoint version of his
conceptual model presentation
2. Mark 7/21 Get Enrico to contribute to expanding the
transformation model in Jin's presentation
3. Steve 7/21 Send memos from CHDStd on hierarchy tracking
mechanisms
Open action items:
Who When What
---------- ------ --------
1. Greg 6/22 First draft of taxonomy for exceptions
-> 7/21
2. Steve 6/22 First draft of taxonomy for parasitics
-> 7/21 boundary conditions
3. Jin 6/22 First draft of taxonomy for timing boundary
-> 7/21 conditions
4. Greg 6/22 Write up an extended description of how tags work
-> 8/4
5. Jim 6/22 Write up an extended description of how operating
-> 7/21 conditions work
6. Mark 7/7 Arrange for a face to face meeting at ICCAD
-> 7/21
7. Mark 7/7 Follow up with Vassilios on legal aspects of
-> 7/21 Ambit donation
8. Mark 7/7 Look into face to face meeting coinciding with
-> 7/21 ISLPED (International Symposium on Low Power
Electronics and Design)
Completed action items:
Who When What
---------- ------ --------
1. Mark 6/22 First draft of taxonomy for clocking
2. Mark 7/7 Add links to other related standards from the
DC-WG web page
3. Jin 7/7 Consolidate presentations on the conceptual
model into a Word document
Details:
1. Constraint taxonomy
We reviewed the first draft of the clock constraints.
People agreed that separating the waveform description from the
assignment of a waveform to a clock root is good.
We discussed whether transition times for clock edges should
be modeled in the waveform description, or treated the same as
transition times for data signals, and agreed on the latter.
Missing things:
- Clock to clock uncertainty
- An ability to override the internal clock insertion delay
(which should be part of the timing model for a block) by
setting the new insertion delay value on the clock input pin
of the block.
We talked about whether there should be commands for removing or
"undo-ing" constraints, and concluded probably not:
- the constraint language should describe the designer's
intent, which is a static thing, not dynamic
- want to have the possibility of passing the same constraint
file to multiple tools in the flow, which doesn't work if
constraints are enabled/disabled based on tool behavior
On the other hand, if designers really do want to dynamically
change the constraints in several different tools, it would be
good to have a consistent way of doing it.
2. Conceptual model
We reviewed Jin's skeleton for the conceptual model document,
which was a great start.
We discussed whether we should try to identify different classes
of constraints. One possibility is to organize them by what type
of design object they apply to (clock, signal, block, ...). Another
possibility that Mark used in the clock taxonomy is to organize
them by their effect (constraints, environment conditions, and
controls).
We agreed that it would be useful to have a glossary or
definitions section in the conceptual model, then discussed
whether this would lead to overlap with a similar section in the
taxonomy. We agreed to start by having two separate sections,
and then look at merging them later if there is a lot of overlap.
We talked about the hierarchy model aspect of the conceptual
model, which is intended to describe transformations on the
hierarchy of the design and the effect of those transformations
on the constraints.
Steve Grouts talked about the approach used in Sematech's CHDStd
project, where the system as a whole provided tracking mechanisms
for hierarchy and netlist modifications. An important issue is
whether the constraints should be transformed along with the
netlist at each step in the flow, or whether the original
constraints should be transformed only when necessary, based on
the entire history of changes up to that point.
3. Timing constraint/environment conditions semantics for interface nets
Dan Moritz asked about the semantics for accounting for how much
wire delay lies on either side of a hierarchy boundary. Mark
had investigated this recently for GCF, and he described the
approach taken in that.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com