If you papers, workshops or turorials please send material through:
www.date-conference.com
Or
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Eugenio Villar
Microelectronics Engineering Group Tel. 34 42 201398
E.T.S.I.Industriales y Telecom. Fax. 34 42 201873
University of Cantabria email. villar@teisa.unican.es
Avda. Los Castros s/n, 39005 Santander, Spain
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Best REgards
Vassilios Gerousis
-------------------Forwarded Message -------------------
This message is to invite you to submit your last research results
and design experiences on Standard Design Languages to Topic B8:
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B8. Standard Design Languages
VHDL/VHDL-AMS and Verilog/Verilog-A design techniques; practical
use of VHDL-AMS and Verilog-A; application studies of standard
design languages; analysis and effective use of new extensions
and subsets of the VHDL and Verilog standards; VHDL and Verilog
interoperability in design projects and design tools; standard
design languages for IP-based design; standard system-level
design languages and SLDL standardization.
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of the Design, Automation & Test in Europe (DATE'99) Conference
to be held in Munich, Germany, 9-12 of March, 1999.
Deadline for paper submission is: September 19, 1998
For additional information about the conference and instructions
to authors, have a look to http://www.date-conference.com
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