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EE Times did an article on the SLDL workshop that I attended,
and DC-WG is discussed as well.
http://www.techweb.com/se/directlink.cgi?EET19980921S0037
Unfortunately, Peter Clarke (an EE Times European correspondent)
didn't check with me on his "quotes". The main inaccuracy is the
statement that DC-WG will be extending the Ambit constraint language
into a General Constraint Format. I definitely didn't say that, since
GCF is the Cadence proprietary tool-to-tool interchange format, not
what DC-WG will produce.
I did say that we would use the Ambit constraint language as a
strawman in defining the DC-WG constraint description language.
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com --------------2BF12A8DBEF95A35C5B1222E Content-Type: text/html; charset=iso-8859-1; name="directlink.cgi" Content-Disposition: inline; filename="directlink.cgi" Content-Base: "http://www.techweb.com/se/directlink.c gi?EET19980921S0037" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by timing.Cadence.COM id JAA28077=20
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September 21, 1998, Issue: 1026 Section: Design Automation Committee speeds industry toward adoption vote in early 2001 -- Schedule = set for system-level design language Peter Clarke
Lausanne, Switzerland - A new design language that could change the w= ay electronic systems are developed has moved into the implementation pha= se, according to participants at a system-level design language (SLDL) wo= rkshop at the recent International Forum on Design Languages here. The SL= DL committee is stepping up activity so industry adoption can begin in th= e first half of 2001. The effort-a high-priority project backed by the EDA Industry Council= -seeks to develop a language that can easily describe complete electronic= systems, including software and hardware, in a formal way that allows co= nstraints to be passed to implementation tools. SLDL does not seek to replace VHDL or Verilog. In fact, over the next= year, links between the SLDL committee and the design-constraints workin= g group of Open Verilog International are likely to be strengthened. The = same holds true for the systems-level development working group of the Vi= rtual Socket Interface (VSI) alliance. Prototyping partnerships will be f= ormed, and a draft language-reference manual will be produced. "The real work starts here," said David Barton, senior computer scien= tist at Intermetrics Inc. (Vienna, Va.) and chairman of the SLDL committe= e. The overall problem the committee faces is large. Stepping up to high= er levels of digital complexity while the effects of process technology g= row more significant is tough enough; but designers also want to integrat= e previously separate domains, including analog, mixed-signal and radio-f= requency design. A number of languages exist, or are coming into existence, to address= different facets of the problem-but often at the price of solving one pa= rt but ignoring others. That creates the risk of compromising the overall= system-design goals. Steve Schulz, senior member of the technical staff at Texas Instrumen= ts Inc.'s advanced ASIC architecture group and chairman of the EDA Indust= ry Council Project Technical Advisory Board, came to the SLDL workshop wi= th a set of proposals, including a development schedule that divides crea= ting the language into two phases. Schulz also offered a set of the model= s of computation that he believes SLDL must support. "We want to have the beginnings of a 'straw-man' definition of the la= nguage by the end of the year, and an initial draft of the Phase I Langua= ge Reference Manual by the third quarter of 1999," said Barton of Interme= trics. "In the last month or two I think we've come to a clearer understandi= ng," said Schulz. "I think it [SLDL] is do-able." Previous SLDL committee work concentrated on defining and studying th= e problem, and has resulted in a requirements document which the subseque= nt phases will seek to meet. Noting that the committee has yet to vote on some of these issues, Ba= rton said it was his opinion that phase one is likely to include the use = of declarative constraints. If and when this can be generalized, it could= allow such things as power-consumption constraints and timing to be incl= uded within high-level specifications and propagated down as part of the = elaboration of the design. Phase two would then contain more generalized semantic work, simulati= on of Phase I SLDL, as well as feedback from prototype-partnership work.<= /P> During the workshop Barton and Schulz repeatedly emphasized that SLDL= could not just be a new language, even with the capabilities to superset= what existing languages already do. Instead, Barton and Schulz said, SLD= L is likely to be a semantic framework and, potentially, a language in it= s own right. In other words, SLDL must be able to model the languages tha= t will be used to model systems, including itself. Schulz said the idea is to be able to model the variety of languages = already coming into use and accurately characterize interfaces among them= , and between them and the outside world-including other modeling domains= , such as thermal or hydraulic. In that way, engineers could continue to = use chosen languages, such as C, C++ or Java, but transfer to other repre= sentations of the system, for example in VHDL or Verilog. The workshop saw presen-tations on many languages in development, inc= luding VHDL- AMS, the analog and mixed-signal extension to VHDL; Suave an= d VHDL+, which add communicating processes, concurrency and protocol-hand= ling to VH-DL; and the Esterel-C language. Barton said the idea of systems design being composed of multiple dom= ains or facets, each being a different view of the system, was a powerful= one. "Domain theories are a major source of models, and of reuse in SLDL= . If we don't address reuse and foreign interfaces early, SLDL will fail = early," Barton warned. "Doing the language is the easiest part of the tas= k, doing the domains and getting them to a point where they can be used i= s the most important thing." But Barton also agreed that progress could depend on developing an in= dustry-wide understanding of system-level terms and their relationships t= o each other. "The glossary is a big part of the SLDL requirements docume= nt," he said, "but we are also looking at the VSI systems-level-developme= nt, working-group taxonomy." Marc Genoe, system-level design methodology manager at Alcatel Microe= lectronics (Brussels) and chairman of that VSI working group, said that i= ts model taxonomy document was being reviewed by committee members and wa= s expected to be available, probably by way of publishing on the VSI Web = site, in mid-October. He said that it was based on a glossary produced by= the U.S. RASSP project on rapid prototyping, but provided a number of ex= tensions to that document. "A number of members of VSI are also working within SLDL," said Genoe= , who sees increasing "convergence" between the two groups. "So I feel th= ere will be more joint work." Genoe said that although nothing had been decided officially, one way= forward would be to allow pilot projects within VSI to also serve as pro= totyping partnerships for the purposes of SLDL. Of more immediate interest could be the Design Constraints Working Gr= oup (DCWG) of Open Verilog International. Mark Hahn, of Cadence Design Systems Inc. (San Jose, Calif.) and chai= rman of DCWG, explained that his group, started in March 1998, has alread= y opened itself up to more than just the interests of the Verilog languag= e. Although formally reporting through the technical coordinating committ= ee of Open Verilog International, it is also sponsored by the VSI allianc= e's implementation and verification working group and has hopes of being = sponsored by VHDL International and the SLDL committee. Hahn said his working group's preference for public-domain and licens= e-free standards prompted a move to adopt the Ambit Constraint Language, = from Ambit Design Systems Inc. (Santa Clara, Calif.) as its starting poin= t. The decision was made after talks with the industry's major suppler of= synthesis tools, Synopsys Inc. (Mountain View, Calif.). Hahn said that Ambit's constraints format now covers timing and clock= constraints, but that the DCWG is planning to extend it into a General C= onstraint Format, which would also cover power, parasitics and signal-int= egrity constraints. "Having a constraints description that is separate to the source desc= ription makes possible the supporting of many different languages. I thin= k the General Constraints Format could be equally applicable to other lan= guages," he said. TI's Schulz said the Language Reference Manual is a fundamental requi= rement enabling development of EDA tools that he hoped could be beta test= ed in 2000. "We won't have new tools as such, but tools extended to meet = the modeling requirements of SLDL," he said. Alain Vachoux, a professor at the Swiss Federal Institute of Technolo= gy and chairman of this year's Forum on Design Languages, of which the SL= DL workshop was a part, said the event replaces the European VHDL Users F= orum. Copyright =AE 1998 CMP Media Inc. =
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