Attendees:
Mark Hahn, Cadence (Chair)
Dave Barton, Intermetrics
Tom Dewey, Mentor Graphics
Ibna Faruque, Synopsys
Vassilios Gerousis, Motorola
Steve Grout, Sematech
Dan Moritz, LSI Logic
Greg Schulte, Cadence (formerly Ambit)
Jim Swift, IBM
Andres Teene, LSI Logic (formerly Symbios)
New action items:
Who When What
---------- ------ --------
1. Jim 10/27 Check whether there are any patents which
might affect the IBM strawman donation
2. Jim 10/27 Investigate whether the strawman would include
just the Einstimer command reference or also the
introductory manual and educational material
3. Vassilios 10/27 Provide IBM with a copy of the template for
transferring copyright to OVI
4. Mark 10/27 Coordinate first couple of meetings for the
joint DC-WG/SLDL sub-committee
5. Mark, Steve 10/27 Create a reflector and web site for the joint
sub-committee
6. Mark 10/27 Create a diagram showing the relationship between
DC-WG and SLDL
7. Mark, Greg 10/27 Come up with a proposal for the semantics of
how source latency and jitter, common ambiguity,
common jitter, and inter-clock uncertainty relate
8. Dan 10/27 Give feedback to Steve Grout about parasitics
boundary conditions
9. Mark 10/27 Split taxonomy document into sub-documents
for each major section
10. Mark, Dan 10/27 Refine the task breakdown, updating it to reflect
the DC-WG/SLDL sub-committee
11. Mark 10/27 Talk with Larry Pillegi about potential DC-WG
activities at Tau '99
Open action items:
Who When What
---------- ------ --------
1. Jin, Jim 8/25 Discuss PVT-dependent constraints and relationship
to conceptual model
-> Need to reassign
2. Jim 9/15 Investigate IBM strawman possibility
-> 9/29
-> 10/13
-> 10/27
3. Jim 10/13 Add operating conditions to the taxonomy
-> 10/27
4. Mark 10/13 Schedule a face to face meeting at ICCAD
-> 10/27
Closed action items:
Who When What
---------- ------ --------
1. Mark 10/13 Set up the web site to make the latest copy of the
taxonomy directly accessible
Next Meeting:
The next meeting will be a teleconference on
Tuesday, 10/27/98, from 9-11 am PDT.
Details:
1. Review progress on action items
Jim Swift has been working on getting approval for the IBM strawman.
The manager of the Einstimer group agreed to provide a memo
and a scrubbed document by 10/16. Vassilios will provide the
template for copyright transfer to use as the basis for that memo.
We discussed what documentation would be provided. Dan Moritz
suggested that it would be very helpful if we could get the
introductory manual as well as some additional background
material; Jim will check into this.
There hasn't been any progress yet on the operating conditions
section of the taxonomy.
Mark has been trying to set up the face to face meeting at ICCAD;
it will probably be during the lunch break. If we can't get a
room at the Doubletree hotel, it will be at a local company nearby.
2. Discuss proposed relationship with SLDL
We discussed this at length. Steve Grout was concerned about the
potential separation between the constraint description language
defined by DC-WG and the system-level design language defined by
the SLDL group. Dave Barton thought that the constraints portion
of the SLDL language should be fairly separable and that it would
probably be straightforward to convert one form into the other even
if syntax wasn't identical. There was some concern that the strawman
proposals for DC-WG are command language-oriented, while the SLDL
language may take a different form.
We took a formal vote, and the proposal to form a joint sub-committee
was unanimously approved.
There were some concerns about the DC-WG schedule and whether it
would be possible to develop production capabilities for DAC around
the DC-WG standard; this was not the intent for the DAC demos.
We talked about the need to participate in the conferences leading
up to DAC. The Tau '99 workshop in March is a good example, as is
the HDL conference in early April.
3. Discuss clock, boundary parasitics sections
in taxonomy
We talked about changes to the clock contraints section. For
partial clock trees contained within a hierarchical block, it
is useful to have a constraint on their insertion delay, which
is used in creating the partial tree. Before the partial tree
is created, the constraint can be used as the worst case bounds
for an estimate. After the partial tree is created, the constraint
value could be updated to reflect the actual insertion delay. In
that case, if the timing model for the hierarchical block did not
describe the internal insertion delay, or the user wanted to explore
different hierarchical clock budgets, the constraint value could
be used instead of the vale from the timing model.
We also talked about clock to clock uncertainty, and agreed that
the semantics need to be more clearly defined for how that
uncertainty relates to explicitly defined insertion delays and
jitter on the "from" and "to" clocks. Clock to clock uncertainty
should only be used when the from and to clocks are in the same
domain, which implies that they're derived from a common oscillator.
In that case, some portion of the overall clock distribution network
is common to the two, potentially reducing skew and jitter.
We briefly discussed the boundary parasitics section, and Dan and
Mark promised to provide feedback to Steve.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com