please consider submission of your papers to the FDL'99 - the
International Forum on Design Languages that will be held in the Ecole
Normale Superieure de Lyon, Aug 30-Sept 3,1999. FDL'99 is composed of
three topical workshops:
* FDL Workshop with VHDL Users' Forum in Europe (Aug. 31-Sept.1)
* Workshop on Virtual Component Design & Reuse (Sept. 1-2)
and
* Workshop on System Specification & Design Languages (Sept.2-3)
Please find below the FDL'99 Call for Papers.
With best regards,
Lech Jozwiak
FDL'99 Program Committee Member
_____________________________________________________________________
This message contains public information, only, and the receiver
is allowed, and invited, to copy it and distribute it further.
Our apologies if you received duplicates of this message due to the
mailing list aliases.
You can also visit the FDL'99 web site at
http://www.ecsi/org/ecsi/fdl
The ECSI Team
_______________________________________________________________________
*******************************************************************
* FDL'99 *
* FORUM ON DESIGN LANGUAGES *
* HDL Workshop with VHDL Users' Forum in Europe (Aug. 31-Sept.1) *
* Workshop on Virtual Component Design & Reuse (Sept. 1-2) *
* Workshop on System Specification & Design Languages (Sept.2-3) *
* Ecole Normale Superieure de Lyon, Aug 30-Sept 3,1999 *
*******************************************************************
A SIG-VHDL event sponsored by ECSI, co-sponsored by IFIP 10.5, VI,
OVI, ITG, GI, GMM featuring
CALL FOR CONTRIBUTIONS
_____________________________________________________________________
The Forum on Design Languages (FDL) is the European forum to ex-change
experiences and to learn about new efforts and trends in the
appli-cation of languages and their associated design methods and
tools in mi-cro-electronic design. It is a multi-facetted event that
offers a wonderful opportunity to get up-to-date information thanks to
hosting several events at the same time and the same location, namely:
The HDL Workshop with the VHDL Users' Forum in Europe (HDL&VUFE) is
the European event that gathers together VHDL and other HDL users. It
provides a complete snapshot of the status of the practical use of the
VHDL and other hardware description languages in the electronic design
community, covering the aspects of (formal) specification, modeling,
simulation, synthesis, and testing. It also provides an update on the
latest developments and trends in the evolution of these languages
through standardization projects, and an opportunity to contribute to
these efforts.
The Workshop on Virtual Component Design & Reuse (VCDR) follows up two
occurrences of the Workshop Reuse Techniques for VLSI Design in
Karlsruhe in 1997 and 1998. It is the annual event dedicated to a
broad spectrum of digital and analog VC reuse. The main objective is
to present new ideas and methodologies for reuse and IP. Contributions
from industry and research institutions will be presented from the
do-mains of commercial systems, upcoming development trends and
stan-dardization activities.
The workshop addresses all aspects of research and development for
de-sign reuse and VCs at all relevant levels of abstraction.
The Workshop on System Specification & Design Languages (SSDL)
continues the SLDL workshop held 4 times (Dallas-1996, Santa
Clara-1997, Barga-1997, Lausanne-1998) and is aimed at becoming THE
yearly event on this subject.
It addresses the need to develop industry-wide consensus on the key
problems met by the designers of Systems on a Chip (SoC) as they
relate to e.g. the description of design specification, functional and
implementa-tion constraints, usability by EDA tools. It aims at
developing coordinated industry standards.
The workshop will address all topics relevant to the SoC's, that can
in-clude digital hardware, analog hardware, software, sensors, micro-
me-chanical components (MEMs), batteries, chemical captors, optical
devices.
In addition, the Forum will provide several tutorials on selected hot
topics before the technical sessions and several hands-on tutorials in
parallel with technical sessions. These will allow attendees to try
EDA tools with the help of instructors from EDA companies.
Finally, the Forum will also host several working groups meetings of
the IEEE Design Automation Standards Committee (DASC). These meetings
are open to everybody interested.
TOPICS OF INTEREST
Authors are invited to submit original technical contributions
describing methods, tools, and design practices...
see: http://www.ecsi.org/ecsi/fdl for the list of topics
PRE-FORUM TUTORIALS
Proposals for half-day tutorials are invited.
Proposals will be selected on the evidence that they can transfer in 5
hours a comprehensive knowledge of the topics of interest they are
addressing.
PANEL SESSIONS
Proposals for panels should clearly state the topic, a title, the
composition of panel members and, if available, the name of the
panelists, their affiliations and domain of expertise. The panels will
last no more than one hour and 30 minutes and involve an average of 4
panelists and a moderator.
HANDS-ON-LABS AND WORKING GROUP MEETINGS
Hands-on-labs from EDA tool providers (commercial and academic) are
invited to be given on Unix or PC workstations, in parallel with
technical sessions. A title and a summary of the lab contents are
required.
Working group meetings are welcome, in conjunction with the event or
on Saturday Sept. 4. Applications should be directed to the FDL
Organization Co-Chair as soon as possible to facilitate room
allocation.
REQUIREMENTS FOR SUBMISSION OF CONTRIBUTIONS
Each submission should include a cover page and the proposed
contribution. The cover page should include the complete coordinates
of each author, and the name of the presenter if the contribution is
accepted. The contribution should include
1- the name of the workshop (HDL & VUFE, VCDR, SSDL) and a list of
topics that most closely match its con-tent,
2- a title, and
3- either an extended abstract of approximately 1000-2000 words
(abstracts not in this format will be rejected),
or a full paper not exceeding 10 pages in 12pt, one column format.
Contributions must include descriptions of key ideas, results,
contributions, limitations, experimental condi-tions (if applicable),
and appropriate references to other related works.
Some outstanding late contributions can be submitted until July 2.
Late contributions will not exceed 20% of all accepted contributions.
Accepted authors are NOT required to prepare a full-length final
paper. Slide handouts are accepted as final versions for contributions
that have been submitted as an extended abstract. Abstract-only final
versions are also accepted for confidential presentations that are
subject to non-disclosure constraints. Accepted contribu-tions will be
bound and distributed at the Forum. The best accepted papers will be
candidate to be published in an edited book (publisher yet to be
announced).
FORM OF SUBMISSIONS
Interested authors are invited to send the re-quested information in
electronic format to both
Jean Mermet, FDL General Chair and
Ralf Seepold, FDL Program Chair
Preferred electronic formats are in this order:
PDF, RTF, Postscript,
Compressed submissions with GNU gzip, Unix compress, PKZip are also
accepted.
______________________________________________________________________
IMPORTANT DATES IN 1999
Paper or abstract contributions due March 26
Panel session & tutorial proposals May 7
Notification of acceptance June 4
Final paper contributions due July 2
Late contributions July 2
FDL'99 Aug 30-Sept. 3
Half-day tutorials August 30
HDL & VUFE Aug. 31-Sept. 1
VCDR September 1-2
SSDL September 2-3
______________________________________________________________________
CONTACT POINTS
FDL GENERAL CHAIR
Dr. Jean Mermet
Laboratoire TIMA
ECSI, Parc Equation
France
jean.mermet@imag.fr
FDL ORGANIZATION CO-CHAIR
Dr. Anne Mignotte
Ecole Normale Supérieure de Lyon
France
anne.mignotte@ens-lyon.fr
FDL PROGRAM CHAIR
Dr. Ralf Seepold
FZI Karlsruhe
Germany
seepold@fzi.de
HDL & VUFE CHAIR
Prof. Donatella Sciuto
Politecnico di Milano
Italy
sciuto@elet.polimi.it
VCDR CHAIR
Dr. Ralf Seepold
SSDL CHAIR
Prof. Eugenio Villar
Univ. of Cantabria
Spain
villar@teisa.unican.es
TUTORIAL CHAIR
Prof. Wolfgang Rosenstiel
Universitaet Tuebingen
Germany
rrosenstiel@informatik.uni-tuebingen.de
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I
* * S European CAD Standardization Initiative
* C* Parc Equation, 2 Av. de Vignate, F-38610 GIERES, France
* E * Tel. +33 476 63 49 34, Fax. +33 476 42 87 87
* * Email: office@ecsi.alpes-net.fr
* * Home Page: http://www.ecsi.org
* *
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