DC-WG: RE: DC-WG/SLDL: Agenda for 1/12 teleconference

Steve.Grout@sematech.org
Tue, 12 Jan 1999 10:17:01 -0600

Messages sorted by: [ date ][ thread ][ subject ][ author ]
Next message: Vassilios Gerousis: "DC-WG: Voting On Cadence Proposal"
Previous message: David Barton: "DC-WG: DCDL and the SLDL constraint language"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

--Boundary_(ID_boNMOLyIxiW0Ryoi4jyDqg)
Content-type: text/plain; charset=iso-8859-1

Mark - re the status of my generating constraints definitions
for boundary parasitics, I attach an .rtf of a new edition
though still incomplete document, in the belief it will help to
get feedback on both the definitions that I have completed so
far, as well as the grouping of the terms.

It is coming together though I still spend a lot of time simply
rewriting and re-sorting them. The formatting now is per your
template (actually I still cheat slightly in that the matrix
is portrait and not landscape so I can edit in a window more
easily.) Note that I am continuing to carry the Ambit strawman
definitions as indented and as-is for reference by any reviewers

It IS coming together steadily now and I spend an hour or better on
it each evening.

I feel I am on the downhill now and should complete it by next Tuesday.

Please tell me if you were able to successfully read the attached file.
I would also greatly appreciate anyone's feedback on my approach to
the definitions, especially the main semantic definition. I would also
of course appreciate feedback on any other boundary parasitics that
this section should address.

Regards,
--Steve Grout
Sematech

>
> --
> Mark Hahn phone:
> (408) 428-5399
> Architect, Deep Submicron Business Unit fax:
> (408) 428-5959
> Cadence Design Systems email:
> mhahn@cadence.com
>

--Boundary_(ID_boNMOLyIxiW0Ryoi4jyDqg)
Content-type: application/rtf; name=Parasitics07sg.rtf
Content-disposition: attachment; filename=Parasitics07sg.rtf
Content-transfer-encoding: quoted-printable
Content-Location: ATT-0-2A18F2742AAAD211A9FB0001FA7EC64E-P ACADC%7E1.RTF

{\rtf1\ansi\ansicpg1252\uc1 =
\deff0\deflang1033\deflangfe1033{\fonttbl{\f0\froman\fcharset0\fprq2{\*\=
panose 02020603050405020304}Times New =
Roman;}{\f1\fswiss\fcharset0\fprq2{\*\panose =
020b0604020202020204}Arial;}
{\f2\fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier =
New;}{\f3\froman\fcharset2\fprq2{\*\panose =
05050102010706020507}Symbol;}{\f4\froman\fcharset0\fprq2{\*\panose =
12000000000016000000}TIMES;}
{\f5\fswiss\fcharset0\fprq2{\*\panose =
020b0604020202020204}Helvetica;}{\f6\fmodern\fcharset0\fprq1{\*\panose =
00000000000000000000}Courier{\*\falt Courier =
New};}{\f7\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Geneva;}
{\f8\froman\fcharset0\fprq2{\*\panose 00000000000000000000}Tms =
Rmn{\*\falt Times New Roman};}{\f9\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Helv;}{\f10\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}MS Serif;}
{\f11\fswiss\fcharset0\fprq2{\*\panose 00000000000000000000}MS Sans =
Serif;}{\f12\froman\fcharset0\fprq2{\*\panose 00000000000000000000}New =
York;}{\f13\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}System;}
{\f14\fnil\fcharset2\fprq2{\*\panose =
05000000000000000000}Wingdings;}{\f15\fswiss\fcharset0\fprq2{\*\panose =
020b0604030504040204}Tahoma;}{\f16\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}Palatino;}
{\f17\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}NewCenturySchlbk;}{\f18\froman\fcharset0\fprq0{\*\p=
anose =
00000000000000000000}Times-Roman;}{\f19\froman\fcharset0\fprq0{\*\panose=
00000000000000000000}Times-Italic;}
{\f20\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}AvantGarde;}{\f21\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}ITC =
Bookman;}{\f22\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Helvetica-Condensed;}
{\f23\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Helvetica-Narrow;}{\f24\froman\fcharset0\fprq2{\*\p=
anose =
00000000000000000000}ZapfChancery;}{\f25\fdecor\fcharset2\fprq2{\*\panos=
e 00000000000000000000}ZapfDingbats;}
{\f26\fnil\fcharset2\fprq2{\*\panose =
00000000000000000000}Marlett;}{\f27\fmodern\fcharset0\fprq1{\*\panose =
020b0609040504020204}Lucida =
Console;}{\f28\fswiss\fcharset0\fprq2{\*\panose =
020b0602030504020204}Lucida Sans Unicode;}
{\f29\froman\fcharset0\fprq2{\*\panose 02040602050305030304}Book =
Antiqua;}{\f30\fnil\fcharset2\fprq2{\*\panose =
01010601010101010101}Monotype =
Sorts;}{\f31\fswiss\fcharset0\fprq2{\*\panose =
020b0506020202030204}Arial Narrow;}
{\f32\froman\fcharset0\fprq2{\*\panose 02050604050505020204}Bookman Old =
Style;}{\f33\fswiss\fcharset0\fprq2{\*\panose =
020b0502020202020204}Century =
Gothic;}{\f34\fscript\fcharset0\fprq2{\*\panose =
03010101010201010101}Monotype Corsiva;}
{\f35\froman\fcharset0\fprq2{\*\panose 02040604050505020304}Century =
Schoolbook;}{\f36\froman\fcharset2\fprq2{\*\panose =
05050102010205020202}MT Extra;}{\f37\fdecor\fcharset0\fprq2{\*\panose =
04020705040a02060702}Algerian;}
{\f38\fswiss\fcharset0\fprq2{\*\panose 020f0704030504030204}Arial =
Rounded MT Bold;}{\f39\fdecor\fcharset0\fprq2{\*\panose =
04030b070d0b02020403}Braggadocio;}{\f40\fswiss\fcharset0\fprq2{\*\panose=
020b0903060703020204}Britannic Bold;}
{\f41\fscript\fcharset0\fprq2{\*\panose 03060802040406070304}Brush =
Script MT;}{\f42\fdecor\fcharset0\fprq2{\*\panose =
04020805060202030203}Colonna MT;}{\f43\fdecor\fcharset0\fprq2{\*\panose =
04020505020e03040504}Desdemona;}
{\f44\froman\fcharset0\fprq2{\*\panose 0204060206030a020304}Footlight =
MT Light;}{\f45\fswiss\fcharset0\fprq2{\*\panose =
020b0806030902050204}Impact;}{\f46\fdecor\fcharset0\fprq2{\*\panose =
040307050d0c02020703}Kino MT;}
{\f47\froman\fcharset0\fprq2{\*\panose 020a0a07050505020404}Wide =
Latin;}{\f48\fscript\fcharset0\fprq2{\*\panose =
03020802060602070202}Matura MT Script =
Capitals;}{\f49\fdecor\fcharset0\fprq2{\*\panose =
040506030a0602020202}Playbill;}
{\f50\fswiss\fcharset0\fprq2{\*\panose 020b0a04020102020204}Arial =
Black;}{\f51\froman\fcharset0\fprq2{\*\panose 00050102010706020507}Map =
Symbols;}{\f52\froman\fcharset0\fprq2{\*\panose =
02020404030301010803}Garamond;}
{\f53\fscript\fcharset0\fprq2{\*\panose 030f0702030302020204}Comic Sans =
MS;}{\f54\fswiss\fcharset0\fprq2{\*\panose =
020b0604030504040204}Verdana;}{\f55\froman\fcharset2\fprq2{\*\panose =
05030102010509060703}Webdings;}
{\f56\froman\fcharset0\fprq2{\*\panose =
02040502050405020303}Georgia;}{\f57\fswiss\fcharset0\fprq2{\*\panose =
020b0603020202020204}Trebuchet =
MS;}{\f58\fmodern\fcharset0\fprq2{\*\panose =
020b0509000000000004}Monotype.com;}
{\f59\froman\fcharset0\fprq2{\*\panose 02040503050201020203}Minion =
Web;}{\f60\fnil\fcharset2\fprq2{\*\panose 05000000000000000000}MS =
Outlook;}{\f61\fswiss\fcharset0\fprq2{\*\panose =
020e0602030304020304}Albertus Medium;}
{\f62\fswiss\fcharset0\fprq2{\*\panose 020e0802040304020204}Albertus =
Extra Bold;}{\f63\fswiss\fcharset0\fprq2{\*\panose =
020b0603020204030204}Antique =
Olive;}{\f64\fswiss\fcharset0\fprq2{\*\panose 020b0502050508020304}CG =
Omega;}
{\f65\froman\fcharset0\fprq2{\*\panose 02020603050405020304}CG =
Times;}{\f66\froman\fcharset0\fprq2{\*\panose =
02040706040705040204}Clarendon =
Condensed;}{\f67\fscript\fcharset0\fprq2{\*\panose =
03030502040406070605}Coronet;}
{\f68\fmodern\fcharset0\fprq1{\*\panose 020b0409020202030204}Letter =
Gothic;}{\f69\fscript\fcharset0\fprq2{\*\panose =
03020702040402020504}Marigold;}{\f70\fswiss\fcharset0\fprq2{\*\panose =
020b0603020202030204}Univers;}
{\f71\fswiss\fcharset0\fprq2{\*\panose 020b0606020202060204}Univers =
Condensed;}{\f72\fswiss\fcharset0\fprq2{\*\panose =
020b0a04020102020204}Arial MT =
Black;}{\f73\fscript\fcharset0\fprq2{\*\panose =
03060802030402020204}Benguiat Frisky;}
{\f74\fdecor\fcharset0\fprq2{\*\panose =
04020905020d02060204}Bertram;}{\f75\fdecor\fcharset0\fprq2{\*\panose =
040c09040503070d0203}Challenge Extra =
Bold;}{\f76\fswiss\fcharset0\fprq2{\*\panose =
020f0804020102020204}Glowworm;}
{\f77\fscript\fcharset0\fprq2{\*\panose 03020402050402020203}Graphite =
Light;}{\f78\fscript\fcharset0\fprq2{\*\panose =
03010604040201010104}Lucida =
Casual;}{\f79\fnil\fcharset2\fprq2{\*\panose =
05010101010101010101}Milestones;}
{\f80\fscript\fcharset0\fprq2{\*\panose =
03020902050305070206}Nadianne;}{\f81\fnil\fcharset0\fprq2{\*\panose =
02010502050601010104}Old =
English;}{\f82\fdecor\fcharset0\fprq2{\*\panose =
040103030504070e0101}Party;}
{\f83\froman\fcharset0\fprq2{\*\panose 02070a04080905020204}Poster =
Bodoni;}{\f84\froman\fcharset0\fprq2{\*\panose =
02070402040307030201}Pompeii =
Capitals;}{\f85\fscript\fcharset0\fprq2{\*\panose =
03030602040407090b05}Signet Roundhand;}
{\f86\fswiss\fcharset0\fprq2{\*\panose 020f0706050301020404}Theatre =
Antoine;}{\f87\fdecor\fcharset0\fprq2{\*\panose =
04050602080702020203}Onyx;}{\f88\fnil\fcharset0\fprq2{\*\panose =
00000000000000000000}PG Text;}
{\f89\fnil\fcharset0\fprq2{\*\panose 00000000000000000000}PGMusic =
F;}{\f90\fswiss\fcharset0\fprq2{\*\panose 020b7200000000000000}PG Music =
Font;}{\f91\froman\fcharset0\fprq0{\*\panose =
00000000000000000000}Times-Bold;}
{\f92\froman\fcharset238\fprq2 Times New Roman =
CE;}{\f93\froman\fcharset204\fprq2 Times New Roman =
Cyr;}{\f95\froman\fcharset161\fprq2 Times New Roman =
Greek;}{\f96\froman\fcharset162\fprq2 Times New Roman Tur;}
{\f97\froman\fcharset186\fprq2 Times New Roman =
Baltic;}{\f98\fswiss\fcharset238\fprq2 Arial =
CE;}{\f99\fswiss\fcharset204\fprq2 Arial =
Cyr;}{\f101\fswiss\fcharset161\fprq2 Arial =
Greek;}{\f102\fswiss\fcharset162\fprq2 Arial Tur;}
{\f103\fswiss\fcharset186\fprq2 Arial =
Baltic;}{\f104\fmodern\fcharset238\fprq1 Courier New =
CE;}{\f105\fmodern\fcharset204\fprq1 Courier New =
Cyr;}{\f107\fmodern\fcharset161\fprq1 Courier New =
Greek;}{\f108\fmodern\fcharset162\fprq1 Courier New Tur;}
{\f109\fmodern\fcharset186\fprq1 Courier New =
Baltic;}{\f182\fswiss\fcharset238\fprq2 Tahoma =
CE;}{\f183\fswiss\fcharset204\fprq2 Tahoma =
Cyr;}{\f185\fswiss\fcharset161\fprq2 Tahoma =
Greek;}{\f186\fswiss\fcharset162\fprq2 Tahoma Tur;}
{\f187\fswiss\fcharset186\fprq2 Tahoma =
Baltic;}{\f254\fmodern\fcharset238\fprq1 Lucida Console =
CE;}{\f255\fmodern\fcharset204\fprq1 Lucida Console =
Cyr;}{\f257\fmodern\fcharset161\fprq1 Lucida Console Greek;}
{\f258\fmodern\fcharset162\fprq1 Lucida Console =
Tur;}{\f260\fswiss\fcharset238\fprq2 Lucida Sans Unicode CE;}{\f261\fswi=
ss\fcharset204\fprq2 Lucida Sans Unicode =
Cyr;}{\f263\fswiss\fcharset161\fprq2 Lucida Sans Unicode Greek;}
{\f264\fswiss\fcharset162\fprq2 Lucida Sans Unicode =
Tur;}{\f278\fswiss\fcharset238\fprq2 Arial Narrow =
CE;}{\f279\fswiss\fcharset204\fprq2 Arial Narrow =
Cyr;}{\f281\fswiss\fcharset161\fprq2 Arial Narrow Greek;}
{\f282\fswiss\fcharset162\fprq2 Arial Narrow =
Tur;}{\f283\fswiss\fcharset186\fprq2 Arial Narrow =
Baltic;}{\f284\froman\fcharset238\fprq2 Bookman Old Style =
CE;}{\f285\froman\fcharset204\fprq2 Bookman Old Style Cyr;}
{\f287\froman\fcharset161\fprq2 Bookman Old Style =
Greek;}{\f288\froman\fcharset162\fprq2 Bookman Old Style =
Tur;}{\f289\froman\fcharset186\fprq2 Bookman Old Style =
Baltic;}{\f353\fdecor\fcharset161\fprq2 Desdemona Greek;}
{\f362\fswiss\fcharset238\fprq2 Impact =
CE;}{\f363\fswiss\fcharset204\fprq2 Impact =
Cyr;}{\f365\fswiss\fcharset161\fprq2 Impact =
Greek;}{\f366\fswiss\fcharset162\fprq2 Impact =
Tur;}{\f367\fswiss\fcharset186\fprq2 Impact Baltic;}
{\f392\fswiss\fcharset238\fprq2 Arial Black =
CE;}{\f393\fswiss\fcharset204\fprq2 Arial Black =
Cyr;}{\f395\fswiss\fcharset161\fprq2 Arial Black =
Greek;}{\f396\fswiss\fcharset162\fprq2 Arial Black =
Tur;}{\f397\fswiss\fcharset186\fprq2 Arial Black Baltic;}
{\f404\froman\fcharset238\fprq2 Garamond =
CE;}{\f405\froman\fcharset204\fprq2 Garamond =
Cyr;}{\f407\froman\fcharset161\fprq2 Garamond =
Greek;}{\f408\froman\fcharset162\fprq2 Garamond =
Tur;}{\f409\froman\fcharset186\fprq2 Garamond Baltic;}
{\f410\fscript\fcharset238\fprq2 Comic Sans MS =
CE;}{\f411\fscript\fcharset204\fprq2 Comic Sans MS =
Cyr;}{\f413\fscript\fcharset161\fprq2 Comic Sans MS =
Greek;}{\f414\fscript\fcharset162\fprq2 Comic Sans MS Tur;}
{\f415\fscript\fcharset186\fprq2 Comic Sans MS =
Baltic;}{\f416\fswiss\fcharset238\fprq2 Verdana =
CE;}{\f417\fswiss\fcharset204\fprq2 Verdana =
Cyr;}{\f419\fswiss\fcharset161\fprq2 Verdana =
Greek;}{\f420\fswiss\fcharset162\fprq2 Verdana Tur;}
{\f421\fswiss\fcharset186\fprq2 Verdana =
Baltic;}{\f434\fswiss\fcharset238\fprq2 Trebuchet MS =
CE;}{\f438\fswiss\fcharset162\fprq2 Trebuchet MS =
Tur;}{\f440\fmodern\fcharset238\fprq2 Monotype.com =
CE;}{\f441\fmodern\fcharset204\fprq2 Monotype.com Cyr;}
{\f443\fmodern\fcharset161\fprq2 Monotype.com =
Greek;}{\f444\fmodern\fcharset162\fprq2 Monotype.com =
Tur;}{\f445\fmodern\fcharset186\fprq2 Monotype.com =
Baltic;}{\f446\froman\fcharset238\fprq2 Minion Web =
CE;}{\f450\froman\fcharset162\fprq2 Minion Web Tur;}
{\f451\froman\fcharset186\fprq2 Minion Web =
Baltic;}{\f458\fswiss\fcharset238\fprq2 Albertus Medium =
CE;}{\f462\fswiss\fcharset162\fprq2 Albertus Medium =
Tur;}{\f463\fswiss\fcharset186\fprq2 Albertus Medium Baltic;}
{\f464\fswiss\fcharset238\fprq2 Albertus Extra Bold =
CE;}{\f468\fswiss\fcharset162\fprq2 Albertus Extra Bold =
Tur;}{\f469\fswiss\fcharset186\fprq2 Albertus Extra Bold =
Baltic;}{\f470\fswiss\fcharset238\fprq2 Antique Olive CE;}
{\f474\fswiss\fcharset162\fprq2 Antique Olive =
Tur;}{\f475\fswiss\fcharset186\fprq2 Antique Olive =
Baltic;}{\f476\fswiss\fcharset238\fprq2 CG Omega =
CE;}{\f480\fswiss\fcharset162\fprq2 CG Omega =
Tur;}{\f481\fswiss\fcharset186\fprq2 CG Omega Baltic;}
{\f482\froman\fcharset238\fprq2 CG Times =
CE;}{\f486\froman\fcharset162\fprq2 CG Times =
Tur;}{\f487\froman\fcharset186\fprq2 CG Times =
Baltic;}{\f488\froman\fcharset238\fprq2 Clarendon Condensed =
CE;}{\f492\froman\fcharset162\fprq2 Clarendon Condensed Tur;}
{\f493\froman\fcharset186\fprq2 Clarendon Condensed =
Baltic;}{\f494\fscript\fcharset238\fprq2 Coronet =
CE;}{\f498\fscript\fcharset162\fprq2 Coronet =
Tur;}{\f500\fmodern\fcharset238\fprq1 Letter Gothic =
CE;}{\f504\fmodern\fcharset162\fprq1 Letter Gothic Tur;}
{\f505\fmodern\fcharset186\fprq1 Letter Gothic =
Baltic;}{\f506\fscript\fcharset238\fprq2 Marigold =
CE;}{\f510\fscript\fcharset162\fprq2 Marigold =
Tur;}{\f512\fswiss\fcharset238\fprq2 Univers =
CE;}{\f516\fswiss\fcharset162\fprq2 Univers Tur;}
{\f517\fswiss\fcharset186\fprq2 Univers =
Baltic;}{\f518\fswiss\fcharset238\fprq2 Univers Condensed =
CE;}{\f522\fswiss\fcharset162\fprq2 Univers Condensed =
Tur;}{\f523\fswiss\fcharset186\fprq2 Univers Condensed Baltic;}
{\f524\fswiss\fcharset238\fprq2 Arial MT Black =
CE;}{\f528\fswiss\fcharset162\fprq2 Arial MT Black =
Tur;}{\f530\fscript\fcharset238\fprq2 Benguiat Frisky =
CE;}{\f534\fscript\fcharset162\fprq2 Benguiat Frisky =
Tur;}{\f536\fdecor\fcharset238\fprq2 Bertram CE;}
{\f540\fdecor\fcharset162\fprq2 Bertram =
Tur;}{\f542\fdecor\fcharset238\fprq2 Challenge Extra Bold =
CE;}{\f546\fdecor\fcharset162\fprq2 Challenge Extra Bold =
Tur;}{\f548\fswiss\fcharset238\fprq2 Glowworm =
CE;}{\f552\fswiss\fcharset162\fprq2 Glowworm Tur;}
{\f554\fscript\fcharset238\fprq2 Graphite Light =
CE;}{\f558\fscript\fcharset162\fprq2 Graphite Light =
Tur;}{\f560\fscript\fcharset238\fprq2 Lucida Casual =
CE;}{\f564\fscript\fcharset162\fprq2 Lucida Casual =
Tur;}{\f572\fscript\fcharset238\fprq2 Nadianne CE;}
{\f576\fscript\fcharset162\fprq2 Nadianne =
Tur;}{\f578\fnil\fcharset238\fprq2 Old English =
CE;}{\f582\fnil\fcharset162\fprq2 Old English =
Tur;}{\f584\fdecor\fcharset238\fprq2 Party =
CE;}{\f588\fdecor\fcharset162\fprq2 Party Tur;}
{\f590\froman\fcharset238\fprq2 Poster Bodoni =
CE;}{\f594\froman\fcharset162\fprq2 Poster Bodoni =
Tur;}{\f596\froman\fcharset238\fprq2 Pompeii Capitals =
CE;}{\f600\froman\fcharset162\fprq2 Pompeii Capitals Tur;}
{\f602\fscript\fcharset238\fprq2 Signet Roundhand =
CE;}{\f606\fscript\fcharset162\fprq2 Signet Roundhand =
Tur;}{\f608\fswiss\fcharset238\fprq2 Theatre Antoine =
CE;}{\f612\fswiss\fcharset162\fprq2 Theatre Antoine =
Tur;}{\f614\fdecor\fcharset238\fprq2 Onyx CE;}
{\f617\fdecor\fcharset161\fprq2 Onyx =
Greek;}{\f618\fdecor\fcharset162\fprq2 Onyx =
Tur;}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\=
blue255;\red0\green255\blue0;\red255\green0\blue255;\red255\green0\blue0=
;\red255\green255\blue0;
\red255\green255\blue255;\red0\green0\blue128;\red0\green128\blue128;\re=
d0\green128\blue0;\red128\green0\blue128;\red128\green0\blue0;\red128\gr=
een128\blue0;\red128\green128\blue128;\red192\green192\blue192;}{\styles=
heet{\qj\sb120\widctlpar\adjustright=20
\fs20\cgrid \snext0 =
Normal;}{\s1\qj\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brd=
rs\brdrw30\brsp20 \jclisttab\tx432\ls38\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid \sbasedon0 \snext2 heading =
1;}{\s2\qj\fi-576\li576\sb240\keepn\widctlpar
\jclisttab\tx576\ls38\ilvl1\outlinelevel1\adjustright \b\cgrid =
\sbasedon0 \snext0 heading =
2;}{\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\=
tx780\ls38\ilvl2\outlinelevel2\adjustright \b\cgrid \sbasedon2 \snext0 =
heading 3;}{
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls38\ilvl3\outlinelevel3\adjustright \b\cgrid \sbasedon3 \snext0 =
heading =
4;}{\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilv=
l4\outlinelevel4\adjustright=20
\b\fs22\cgrid \sbasedon0 \snext0 heading =
5;}{\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilv=
l5\outlinelevel5\adjustright \i\fs22\cgrid \sbasedon0 \snext0 heading =
6;}{\s7\qj\fi-1296\li1296\sb240\sa60\widctlpar
\jclisttab\tx1296\ls38\ilvl6\outlinelevel6\adjustright \f1\fs20\cgrid =
\sbasedon0 \snext0 heading =
7;}{\s8\qj\fi-1440\li1440\sb240\sa60\widctlpar\jclisttab\tx1440\ls38\ilv=
l7\outlinelevel7\adjustright \i\f1\fs20\cgrid \sbasedon0 \snext0 =
heading 8;}{
\s9\qj\fi-1584\li1584\sb240\sa60\widctlpar\jclisttab\tx1584\ls38\ilvl8\o=
utlinelevel8\adjustright \b\i\f1\fs18\cgrid \sbasedon0 \snext0 heading =
9;}{\*\cs10 \additive Default Paragraph Font;}{
\s15\qj\fi-360\li547\sb120\widctlpar{\*\pn =
\pnlvlblt\ilvl10\ls2047\pnrnot0\pnf8\pnstart1\pnindent360\pnhang{\pntxtb=
?}}\ls2047\ilvl10\adjustright \cgrid \sbasedon0 \snext15 =
Bullet;}{\*\cs16 \additive \sbasedon10 page number;}{
\s17\sb120\keep\widctlpar\adjustright \fs20\cgrid \snext17 =
CellBody;}{\s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid \snext18 =
CellHeading;}{\s19\qj\li1800\sb240\nowidctlpar\tx3600\adjustright =
\b\f4\fs28\cgrid \sbasedon0 \snext19 Date;}{
\s20\qc\sb240\nowidctlpar\adjustright \b\fs20\cgrid \sbasedon0 \snext0 =
Figure;}{\s21\qj\sb240\sl-219\slmult0\nowidctlpar\tx960\tqr\tx9420\tqr\t=
x9840\adjustright \i\f5\fs18\cgrid \sbasedon0 \snext21 =
footer;}{\s22\sb240\sl-280\slmult0\nowidctlpar
\tx960\tqc\tx4339\tqr\tx8479\adjustright \i\f5\cgrid \snext22 =
Footer_Cover;}{\s23\qj\sb120\sl-219\slmult0\nowidctlpar\tqr\tx8611\tqr\t=
x9840\adjustright \i\f5\fs18\cgrid \sbasedon0 \snext23 =
header;}{\s24\sb360\widctlpar\adjustright \b\caps\f1\cgrid=20
\sbasedon1 \snext0 \sautoupd toc =
1;}{\s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
\sbasedon0 \snext25 =
Name;}{\s26\qj\li1685\sb240\nowidctlpar\tx2880\adjustright =
\i\f4\fs36\cgrid \sbasedon0 \snext26 Revision;}{\s27\qc\sl-280\slmult0
\nowidctlpar\adjustright \b\f4\cf16\cgrid \snext27 =
TableTitle;}{\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adju=
stright \fs20\cf1\cgrid \sbasedon0 \snext30 =
Semantics;}{\s29\qj\fi-360\li547\sb120\widctlpar{\*\pn =
\pnlvlblt\ilvl10\ls2047\pnrnot0
\pnf8\pnstart1\pnindent360\pnhang{\pntxtb ?}}\ls2047\ilvl10\adjustright =
\cgrid \sbasedon15 \snext29 =
Dash;}{\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustrigh=
t \fs20\cf1\cgrid \sbasedon28 \snext30 Type;}{
\s31\li288\sb120\sa120\widctlpar\adjustright \b\fs20\cgrid \sbasedon0 =
\snext31 Parameters;}{\s32\qj\li576\sb120\widctlpar\adjustright =
\fs20\cgrid \sbasedon0 \snext32 =
Parameter;}{\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright=20
\fs20\cf1\cgrid \sbasedon30 \snext34 =
Dependencies;}{\s34\qj\li288\sb120\widctlpar\adjustright \fs20\cgrid =
\sbasedon0 \snext31 =
Verification;}{\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\ad=
justright \fs20\cf1\cgrid \sbasedon30 \snext33=20
Applicability;}{\s36\sb240\widctlpar\adjustright \b\fs20\cgrid =
\sbasedon2 \snext0 \sautoupd toc 2;}{\s37\li200\widctlpar\adjustright =
\fs20\cgrid \sbasedon25 \snext0 \sautoupd toc =
3;}{\s38\li400\widctlpar\adjustright \fs20\cgrid=20
\sbasedon28 \snext0 \sautoupd toc 4;}{\s39\li600\widctlpar\adjustright =
\fs20\cgrid \sbasedon0 \snext0 \sautoupd toc =
5;}{\s40\li800\widctlpar\adjustright \fs20\cgrid \sbasedon0 \snext0 =
\sautoupd toc 6;}{\s41\li1000\widctlpar\adjustright \fs20\cgrid=20
\sbasedon0 \snext0 \sautoupd toc 7;}{\s42\li1200\widctlpar\adjustright =
\fs20\cgrid \sbasedon0 \snext0 \sautoupd toc =
8;}{\s43\li1400\widctlpar\adjustright \fs20\cgrid \sbasedon0 \snext0 =
\sautoupd toc 9;}{\s44\qj\fi-360\li360\sb120\widctlpar
\jclisttab\tx360{\*\pn \pnlvlbody\ilvl0\ls30\pnrnot0\pndec =
}\ls30\adjustright \fs20\cgrid \sbasedon0 \snext44 \sautoupd List =
Bullet;}{\s45\qj\sb120\widctlpar\adjustright \fs20\cgrid \sbasedon0 =
\snext45 footnote text;}{\*\cs46 \additive \super \sbasedon10=20
footnote =
reference;}}{\*\listtable{\list\listtemplateid933021884\listsimple{\list=
level\levelnfc23\leveljc0\levelfollow0\levelstartat1\levelspace0\levelin=
dent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 =
\fi-360\li360\jclisttab\tx360 }{\listname=20
;}\listid-119}{\list\listtemplateid-1\listsimple{\listlevel\levelnfc0\le=
veljc0\levelfollow0\levelstartat0\levelspace0\levelindent0{\leveltext\'0=
1*;}{\levelnumbers;}}{\listname =
;}\listid-2}{\list\listtemplateid-1994766790{\listlevel\levelnfc0\levelj=
c0
\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;=
}{\levelnumbers\'01;}\fbias0 \fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers
\'01\'03;}\fbias0 \fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-825\li825\jclisttab\tx825 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext=
\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat2\levelspace0\l=
evelindent0
{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\=
'09;}\fbias0 \fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0=
b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid191186669}{\list\listtemplateid-1323032202{\listlevel\levelnfc0=
\leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-645\li645\jclisttab\tx645 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat6\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-645\li645\jclisttab\tx645 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat4\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid318072166}{\list\listtemplateid-546672396{\listlevel\levelnfc0\=
leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\=
'01\'00;}{\levelnumbers\'01;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\'03\'00.=
\'01;}{\levelnumbers\'01\'03;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat4\levelspace0\l=
evelindent0{\leveltext
\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0=20
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'=
03\'05\'07\'09;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0=
b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1
\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'=
06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0 =
\fi-1080\li1080\jclisttab\tx1080 }{\listlevel\levelnfc0\leveljc0\levelfo=
llow0\levelstartat1\levelspace0\levelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid352266652}{\list\listtemplateid-871755498{\listlevel\levelnfc0\=
leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-495\li495\jclisttab\tx495 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat6\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-495\li495\jclisttab\tx495 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat4\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid413623908}{\list\listtemplateid-452158166{\listlevel\levelnfc0\=
leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\=
'01\'00;}{\levelnumbers\'01;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat4\levelspace0\levelindent0{\leveltext\'03\'00.=
\'01;}{\levelnumbers\'01\'03;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0=20
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'=
03\'05\'07\'09;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0=
b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1
\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'=
06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1800\li1800\jclisttab\tx1800 =
}{\listname =
;}\listid624891100}{\list\listtemplateid-1559598540\listsimple{\listleve=
l\levelnfc23\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\u-39=
13 ?;}{\levelnumbers;}\f3\fbias0 \s44\fi-360\li360\jclisttab\tx360 =
}{\listname =
;}\listid759909709}{\list\listtemplateid867884618\listsimple{\listlevel\=
levelnfc0\leveljc0\levelfollow0
\levelstartat0\levelold\levelspace0\levelindent0{\leveltext\'01\'00;}{\l=
evelnumbers\'01;}}{\listname =
;}\listid1033190212}{\list\listtemplateid1399343956{\listlevel\levelnfc0=
\leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext=

\'01\'00;}{\levelnumbers\'01;}\fbias0 \fi-405\li405\jclisttab\tx405 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\fbias0 =
\fi-405\li405\jclisttab\tx405 }{\listlevel
\levelnfc0\leveljc0\levelfollow0\levelstartat7\levelspace0\levelindent0{=
\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0
{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbi=
as0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers
\'01\'03\'05\'07\'09;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\=
'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080
\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0 =
\fi-1080\li1080\jclisttab\tx1080 }{\listlevel
\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{=
\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'0=
1\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.=
\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\=
'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname ;}\listid1058020587}
{\list\listtemplateid-1\listsimple{\listlevel\levelnfc23\leveljc0\levelf=
ollow0\levelstartat1\levelold\levelspace0\levelindent360{\leveltext\'01\=
u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li360 }{\listname =
;}\listid1059131801}
{\list\listtemplateid-1397715328{\listlevel\levelnfc0\leveljc0\levelfoll=
ow0\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnu=
mbers\'01;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat5\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid1091587701}{\list\listtemplateid867884618\listsimple{\listlevel=
\levelnfc0\leveljc0
\levelfollow0\levelstartat0\levelold\levelspace0\levelindent0{\leveltext=
\'01\'00;}{\levelnumbers\'01;}}{\listname =
;}\listid1155221946}{\list\listtemplateid-1350535990{\listlevel\levelnfc=
0\leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0
{\leveltext\'01\'00;}{\levelnumbers\'01;}\fbias0 =
\fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\fbias0 =
\fi-780\li780\jclisttab\tx780 }
{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\le=
velindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fb=
ias0 \fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat2\levelspace0
\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\=
'05\'07;}\fbias0 \fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid1365013427}{\list\listtemplateid-421781932\listsimple{\listleve=
l\levelnfc0\leveljc0\levelfollow0\levelstartat0\levelold\levelspace0\lev=
elindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}\f5\fbias0 =
}{\listname ;}\listid1585798300}
{\list\listtemplateid665607334{\listlevel\levelnfc0\leveljc0\levelfollow=
0\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumb=
ers\'01;}\fbias0 \fi-570\li570\jclisttab\tx570 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat7
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\fbias0 \fi-570\li570\jclisttab\tx570 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid1621764969}{\list\listtemplateid304529758{\listlevel\levelnfc0\=
leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid1780367330}{\list\listtemplateid867884618\listsimple{\listlevel=
\levelnfc0\leveljc0\levelfollow0\levelstartat0\levelold\levelspace0\leve=
lindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}}{\listname =
;}\listid1833792569}
{\list\listtemplateid237912794{\listlevel\levelnfc0\leveljc0\levelfollow=
0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumb=
ers\'01;}\s1\fi-432\li432\jclisttab\tx432 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\b\i0 \s2\fi-576\li576\jclisttab\tx576 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers
\'01\'03\'05;}\s3\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\s4\fi-864\li864\jclisttab\tx864 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\s5\fi=
-1008\li1008\jclisttab\tx1008 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\s6\fi-1152\li1152\jclisttab\tx1152 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\s7\fi-1296\li1296\jclisttab\tx1296 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\s8\fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\s9\fi-1584\li1584\jclisttab\tx1584 =
}{\listname =
;}\listid1844272652}{\list\listtemplateid1779308088{\listlevel\levelnfc0=
\leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-870\li870\jclisttab\tx870 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid1887254452}{\list\listtemplateid-1\listsimple{\listlevel\leveln=
fc23\leveljc0\levelfollow0\levelstartat1\levelold\levelspace0\levelinden=
t360{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li360 =
}{\listname=20
;}\listid1938361620}{\list\listtemplateid-421781932\listsimple{\listleve=
l\levelnfc0\leveljc0\levelfollow0\levelstartat0\levelold\levelspace0\lev=
elindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}\f5\fbias0 =
}{\listname ;}\listid2008511004}
{\list\listtemplateid26144796{\listlevel\levelnfc0\leveljc0\levelfollow0=
\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat4
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1800\li1800\jclisttab\tx1800 =
}{\listname =
;}\listid2071222886}}{\*\listoverridetable{\listoverride\listid-119\list=
overridecount0\ls1}
{\listoverride\listid-119\listoverridecount0\ls2}{\listoverride\listid-1=
19\listoverridecount0\ls3}{\listoverride\listid-119\listoverridecount0\l=
s4}{\listoverride\listid-119\listoverridecount0\ls5}{\listoverride\listi=
d-119\listoverridecount0\ls6}
{\listoverride\listid-119\listoverridecount0\ls7}{\listoverride\listid-1=
19\listoverridecount0\ls8}{\listoverride\listid-119\listoverridecount0\l=
s9}{\listoverride\listid-119\listoverridecount0\ls10}{\listoverride\list=
id-119\listoverridecount0\ls11}
{\listoverride\listid-119\listoverridecount0\ls12}{\listoverride\listid-=
119\listoverridecount0\ls13}{\listoverride\listid-119\listoverridecount0=
\ls14}{\listoverride\listid-119\listoverridecount0\ls15}{\listoverride\l=
istid-119\listoverridecount0\ls16}
{\listoverride\listid-119\listoverridecount0\ls17}{\listoverride\listid-=
119\listoverridecount0\ls18}{\listoverride\listid-119\listoverridecount0=
\ls19}{\listoverride\listid-119\listoverridecount0\ls20}{\listoverride\l=
istid-119\listoverridecount0\ls21}
{\listoverride\listid-119\listoverridecount0\ls22}{\listoverride\listid-=
119\listoverridecount0\ls23}{\listoverride\listid-2\listoverridecount1{\=
lfolevel\listoverrideformat{\listlevel\levelnfc23\leveljc0\levelfollow0\=
levelstartat1\levelold\levelspace0
\levelindent360{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 =
\fi-360\li360 =
}}\ls24}{\listoverride\listid1059131801\listoverridecount0\ls25}{\listov=
erride\listid1155221946\listoverridecount0\ls26}{\listoverride\listid103=
3190212
\listoverridecount0\ls27}{\listoverride\listid1938361620\listoverridecou=
nt0\ls28}{\listoverride\listid1833792569\listoverridecount0\ls29}{\listo=
verride\listid759909709\listoverridecount0\ls30}{\listoverride\listid109=
1587701\listoverridecount0\ls31}
{\listoverride\listid1887254452\listoverridecount0\ls32}{\listoverride\l=
istid1621764969\listoverridecount0\ls33}{\listoverride\listid1780367330\=
listoverridecount0\ls34}{\listoverride\listid191186669\listoverridecount=
0\ls35}{\listoverride\listid1058020587
\listoverridecount0\ls36}{\listoverride\listid1365013427\listoverridecou=
nt0\ls37}{\listoverride\listid1844272652\listoverridecount0\ls38}{\listo=
verride\listid352266652\listoverridecount0\ls39}{\listoverride\listid318=
072166\listoverridecount0\ls40}
{\listoverride\listid413623908\listoverridecount0\ls41}{\listoverride\li=
stid624891100\listoverridecount0\ls42}{\listoverride\listid2071222886\li=
stoverridecount0\ls43}{\listoverride\listid2008511004\listoverridecount0=
\ls44}{\listoverride\listid1585798300
\listoverridecount0\ls45}}{\*\revtbl {Unknown;}}{\info{\title =
Functional Specification}{\author Current User}{\operator Steve =
Grout}{\creatim\yr1999\mo1\dy10\hr22\min17}{\revtim\yr1999\mo1\dy11\hr1\=
min17}{\printim\yr1999\mo1\dy10\hr23\min7}{\version45}{\edmins170}
{\nofpages37}{\nofwords7391}{\nofchars42133}{\*\company Cadence Design =
Systems =
INC.}{\nofcharsws51742}{\vern113}}\margl2160\margr1440\margt1685\margb16=
13 =
\widowctrl\ftnbj\aenddoc\ftnrestart\lytprtmet\hyphcaps0\viewkind4\viewsc=
ale100\pgbrdrhead\pgbrdrfoot=20
\fet0\sectd \psz1\linex0\colsx0\titlepg\sectdefaultcl {\header =
\pard\plain =
\s23\qj\sb120\sl-219\slmult0\nowidctlpar\tqr\tx8611\tqr\tx9840\adjustrig=
ht \i\f5\fs18\cgrid {\tab Constraint Taxonomy
\par }}{\footer \pard\plain =
\s21\qj\ri360\sb240\sl-219\slmult0\nowidctlpar\tqc\tx4320\tqr\tx8640\adj=
ustright \i\f5\fs18\cgrid {\field{\*\fldinst { DATE }}{\fldrslt =
{\lang1024 01/10/99}}}{\tab Design Constraints Working Group\tab =
}{\field{\*\fldinst {\cs16=20
PAGE }}{\fldrslt {\cs16\lang1024 2}}}{\b\i0\f4=20
\par }}{\footerf \pard\plain =
\s22\sb240\sl-280\slmult0\nowidctlpar\tx960\tqc\tx4339\tqr\tx8479\adjust=
right \i\f5\cgrid {\tab \tab \tab=20
\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang{\pntxta =
.}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang{\pntxta =
.}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang{\pntxta =
.}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang{\pntxta )}}
{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl8
\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}\pard\plain \li1685\widctlpar\adjustright \fs20\cgrid {\b Constraint =
Taxonomy
\par }\pard\plain \s26\ri893\sb240\nowidctlpar\adjustright =
\i\f4\fs36\cgrid {\fs20 Version 042 - with S Grout pass-6
\par }\pard\plain \li1685\widctlpar\adjustright \fs20\cgrid {\b=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par Design Constraints Working Group}{
\par }\pard\plain \s19\li1800\sb240\nowidctlpar\tx3600\adjustright =
\b\f4\fs28\cgrid {\fs20=20
\par }\pard \s19\sb240\nowidctlpar\tx3420\adjustright {\fs20=20
\par Open Verilog International
\par }\pard \s19\li1685\sb240\nowidctlpar\tx3600\adjustright {\fs20=20
\par }\pard \s19\sb240\nowidctlpar\tx3600\adjustright {\fs20=20
\par Virtual Socket Interface Alliance
\par }\pard\plain \pagebb\widctlpar\adjustright \fs20\cgrid {\b =
Revision History}{
\par }\pard \sb120\widctlpar\adjustright {
\par }\trowd \trqr\trgaph120 \clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx1182\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15=20
\cltxlrtb \cellx2422\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx5162\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb=20
\cellx8645\pard\plain \s18\nowidctlpar\intbl\adjustright =
\b\f4\fs20\cf1\cgrid {Revision\cell }\pard =
\s18\widctlpar\intbl\adjustright {Date\cell Name\cell Comments\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trqr\trgaph120=20
\clvertalt\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 =
\clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx1182\clvertalt\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 =
\clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx2422\clvertalt
\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 =
\clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx5162\clvertalt\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 =
\clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx8645\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 6\cell =
1/5/99\cell Steve Grout\cell Continued entering definitions for =
hierarchical boundary parasitics.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 2\cell =
\cell Steve Grout\cell=20
2d pass list of objects, identify objects with Ambit C/L strawman =
definitions, copied in available Ambit definitions, and adding other =
definitions. Began to define both commands and design objects targeted =
by the commands.\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 1\cell =
\cell Steve Grout\cell First pass of Parasitic Boundary conditions =
\endash=20
discussion of requirements, first list of objects to be defined.\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{0.2\cell 7/6/98\cell Mark Hahn\cell=20
Added a table of contents, clock constraints, and did some =
reformatting\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\trowd \trqr\trgaph120 \clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr
\brdrs\brdrw15 \cltxlrtb \cellx1182\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx2422\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr
\brdrs\brdrw15 \cltxlrtb \cellx5162\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx8645\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {0.1\cell =
6/8/98\cell=20
Mark Hahn\cell Initial Creation\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 1\tab}}\pard\plain =
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls38\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20=20
\sect }\sectd \psz1\sbknone\linex0\colsx0\titlepg\sectdefaultcl =
{\header \pard\plain =
\s23\qj\sb120\sl-219\slmult0\nowidctlpar\tqr\tx8611\tqr\tx9840\adjustrig=
ht \i\f5\fs18\cgrid {\tab Constraint Taxonomy
\par }}{\footer \pard\plain =
\s21\qj\ri360\sb240\sl-219\slmult0\nowidctlpar\tqc\tx4320\tqr\tx8640\adj=
ustright \i\f5\fs18\cgrid {\field{\*\fldinst { DATE }}{\fldrslt =
{\lang1024 01/10/99}}}{\tab Design Constraints Working Group\tab =
}{\field{\*\fldinst {\cs16=20
PAGE }}{\fldrslt {\cs16\lang1024 14}}}{\b\i0\f4=20
\par }}{\footerf \pard\plain =
\s22\sb240\sl-280\slmult0\nowidctlpar\tx960\tqc\tx4339\tqr\tx8479\adjust=
right \i\f5\cgrid {\tab \tab \tab=20
\par }}\pard\plain \s24\sb360\widctlpar\adjustright \b\caps\f1\cgrid =
{\b0\ul \page Table Of Contents }{
\par }\pard \s24\sb360\widctlpar\tx400\tqr\tx8630\adjustright =
{\field\fldedit{\*\fldinst {\b0 TOC \\o "1-7" }}{\fldrslt {\lang1024 =
1\tab Design Constraints \endash Especially Timing Constraints Driving =
Synthesis\tab }{\field{\*\fldinst {\lang1024 PAGEREF=20
_Toc440646101 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300031000000}}}{\fldrslt {\lang1024 =
5}}}{\lang1024=20
\par }\pard\plain \s36\sb240\widctlpar\tx800\tqr\tx8630\adjustright =
\b\fs20\cgrid {\lang1024 1.1\tab (See ParasaticsDiscussion04sg)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646102 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300032000000}}}{\fldrslt {\lang1024 =
5}}}{\lang1024=20
\par 1.2\tab (See ParasaticsDiscussion04sg)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646103 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300033000000}}}{\fldrslt {
\lang1024 5}}}{\lang1024=20
\par 1.3\tab (See ParasaticsDiscussion04sg)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646104 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300034000000}}}{\fldrslt {
\lang1024 5}}}{\lang1024=20
\par 1.4\tab Hierarchical Parasitic Boundary Conditions\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646105 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300035000000}}
}{\fldrslt {\lang1024 6}}}{\lang1024=20
\par }\pard\plain \s37\li200\widctlpar\tx1200\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1\tab Port General Parasitic Boundary =
Conditions\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646106 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300036000000}}}{\fldrslt {\lang1024 =
6}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.1.1\tab Port Capacitance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646107 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300037000000}}}{\fldrslt {\lang1024 =
6}}}{\lang1024=20
\par }\pard\plain \s40\li800\widctlpar\tx2067\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.1.1.1.1}{\lang1024 \tab =
}{\lang1024\cgrid0 Reference only: set_port_capacitance }{\lang1024 =
(Ambit)\tab }{\field{\*\fldinst {\lang1024 PAGEREF=20
_Toc440646108 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300038000000}}}{\fldrslt {\lang1024 =
6}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.1.1.2}{\lang1024 \tab =
}{\lang1024\cgrid0 Port Capacitance Limit}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646109 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100300039000000}}}{\fldrslt {\lang1024 =
7}}}{\lang1024=20
\par }\pard\plain \s40\li800\widctlpar\tx2067\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.1.1.2.1}{\lang1024 \tab =
}{\lang1024\cgrid0 Reference only: set_port_capacitance_limit =
}{\lang1024 (Ambit)\tab }{\field{\*\fldinst {\lang1024 PAGEREF=20
_Toc440646110 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310030000000}}}{\fldrslt {\lang1024 =
8}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.1.3\tab Global Capacitance Limit\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646111 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310031000000}}}{\fldrslt {\lang1024 =
8}}}{\lang1024=20
\par }\pard\plain \s37\li200\widctlpar\tx1200\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2\tab Input Port Specific Parasitic Boundary =
Conditions\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646112 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310032000000}}}{\fldrslt {\lang1024 =
9}}}{\lang1024=20
\par }\pard\plain \s38\li400\widctlpar\tx1400\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.2\tab Input Port External Environment =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646113 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310033000000}}}{\fldrslt {\lang1024 =
9}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.2.1\tab Equivalent External Sources\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646114 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310034000000}}}{\fldrslt {\lang1024 =
9}}}{\lang1024=20
\par 1.4.1.2.2\tab Number External Sources (Ambit \endash =
num_external_sources)\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646115 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310035000000}}}{\fldrslt {\lang1024 =
10}}}{\lang1024=20
\par }\pard\plain \s40\li800\widctlpar\tx2067\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.1.2.2.1}{\lang1024 \tab =
}{\lang1024\cgrid0 Reference only \endash =
set_num_external_sources}{\lang1024 \tab }{\field{\*\fldinst {\lang1024 =
PAGEREF=20
_Toc440646116 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310036000000}}}{\fldrslt {\lang1024 =
10}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.2.3\tab Input Port External Wire Load\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646117 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310037000000}}}{\fldrslt {\lang1024 =
11}}}{\lang1024=20
\par }\pard\plain \s40\li800\widctlpar\tx2067\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.1.2.3.1}{\lang1024 \tab =
}{\lang1024\cgrid0 Reference only: set_port_wire_load}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646118 \\h }{
\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310038000000}}}{\fldrslt {\lang1024 =
11}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.2.4\tab Input Port Wire Load (Ambit)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646119 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100310039000000}}}{\fldrslt {\lang1024 =
12}}}{\lang1024=20
\par }\pard\plain \s38\li400\widctlpar\tx1400\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.3\tab Input Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646120 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320030000000}}}{\fldrslt {\lang1024 =
12}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.1.3.1\tab Input Port Internal =
Capacitance\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646121 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320031000000}}}{\fldrslt {\lang1024 =
12}}}{\lang1024=20
\par 1.4.1.3.2\tab Input Port Internal Capacitance Limit\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646122 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320032000000}
}}{\fldrslt {\lang1024 13}}}{\lang1024=20
\par 1.4.1.3.3\tab Input port drive strength :\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646123 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320033000000}}
}{\fldrslt {\lang1024 13}}}{\lang1024=20
\par 1.4.1.3.4\tab Effective Load Capacity\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646124 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320034000000}}}{\fldrslt {
\lang1024 14}}}{\lang1024=20
\par 1.4.1.3.5\tab Equivalent Load\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc440646125 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320035000000}}}{\fldrslt {
\lang1024 14}}}{\lang1024=20
\par 1.4.1.3.6\tab Input Port Lumped RC parasitic model\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646126 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320036000000}}
}{\fldrslt {\lang1024 15}}}{\lang1024=20
\par 1.4.1.3.7\tab Input Port Distributed Hierarchical Boundary =
Parasitics (Impedance)\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646127 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320037000000}}}{\fldrslt {\lang1024 =
16}}}{\lang1024=20
\par 1.4.1.3.8\tab Unterminated (Open Circuit) Interface Input Port =
Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646128 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320038000000}}}{\fldrslt {\lang1024 =
16}}}{\lang1024=20
\par 1.4.1.3.9\tab Terminated (Loaded) Instance (Occurrence) Input Port =
Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646129 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100320039000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par }\pard \s39\li600\widctlpar\tx1818\tqr\tx8630\adjustright =
{\lang1024 1.4.1.3.10\tab Distributed R-C Input Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646130 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330030000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par 1.4.1.3.11\tab Distributed R-C-L Input Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646131 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330031000000}}}{\fldrslt {\lang1024 =
18}}}{\lang1024=20
\par 1.4.1.3.12\tab Distributed R-C-L-M Input Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646132 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330032000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par }\pard\plain \s37\li200\widctlpar\tx1200\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2\tab Output Port Parasitic Boundary =
Conditions\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646133 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330033000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par }\pard\plain \s38\li400\widctlpar\tx1400\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.1\tab Output port External Environment =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646134 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330034000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.1.1\tab Output Port Wire Load (Ambit)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646135 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330035000000}}}{\fldrslt {\lang1024 =
20}}}{\lang1024=20
\par 1.4.2.1.2\tab Fanout\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646136 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330036000000}}}{\fldrslt {\lang1024 =
20}}}{
\lang1024=20
\par 1.4.2.1.3\tab Fanout Drive\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc440646137 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330037000000}}}{\fldrslt {\lang1024 21
}}}{\lang1024=20
\par 1.4.2.1.4\tab Fanout Load (Ambit)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646138 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330038000000}}}{\fldrslt {
\lang1024 21}}}{\lang1024=20
\par 1.4.2.1.5\tab Fanout Load Limit (Ambit)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646139 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100330039000000}}}{\fldrslt=20
{\lang1024 22}}}{\lang1024=20
\par }{\lang1024\cgrid0 1.4.2.1.6}{\lang1024 \tab }{\lang1024\cgrid0 =
set_fanout_load_limit}{\lang1024 \tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc440646140 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340030000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par 1.4.2.1.7\tab Output Port External Fanout m <redundant?>\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646141 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340031000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par }\pard\plain \s38\li400\widctlpar\tx1400\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.2\tab Output Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646142 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340032000000}}}{\fldrslt {\lang1024 =
24}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.2.1\tab Output Port Equivalent Custom Wire =
Load\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646143 \\h =
}{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340033000000}}}{\fldrslt {\lang1024 =
24}}}{\lang1024=20
\par 1.4.2.2.2\tab Equivalent Custom Wire Load Mode (Ambit)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646144 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340034000000}}}{\fldrslt {\lang1024 =
25}}}{\lang1024=20
\par 1.4.2.2.3\tab Specified Wire Load Model (Ambit)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646145 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340035000000}}
}{\fldrslt {\lang1024 25}}}{\lang1024=20
\par 1.4.2.2.4\tab Output Port Drive Capability\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646146 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340036000000}}
}{\fldrslt {\lang1024 26}}}{\lang1024=20
\par 1.4.2.2.5\tab Cell (Block) Drive (Ambit)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646147 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340037000000}}
}{\fldrslt {\lang1024 26}}}{\lang1024=20
\par 1.4.2.2.6\tab Drive resistance (Ambit)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646148 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340038000000}}}{\fldrslt {
\lang1024 27}}}{\lang1024=20
\par }\pard\plain \s40\li800\widctlpar\tx2067\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.2.2.6.1}{\lang1024 \tab =
}{\lang1024\cgrid0 set_drive_resistance}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646149 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340039000000}}}{\fldrslt {\lang1024 =
28}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.2.7\tab Available Drive\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646150 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350030000000}}}{\fldrslt {\lang1024 =
28}}}{\lang1024=20
\par 1.4.2.2.8\tab Output port Drive Strength:\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646151 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350031000000}}
}{\fldrslt {\lang1024 29}}}{\lang1024=20
\par 1.4.2.2.9\tab Output Port Internal Capacitance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646152 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350032000000}}
}{\fldrslt {\lang1024 29}}}{\lang1024=20
\par }\pard \s39\li600\widctlpar\tx1818\tqr\tx8630\adjustright =
{\lang1024 1.4.2.2.10\tab Output Port Internal Capacitance Limit\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646153 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350033000000}}}{\fldrslt {\lang1024 =
30}}}{\lang1024=20
\par 1.4.2.2.11\tab Effective Drive Internal Capacitance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646154 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350034000000}
}}{\fldrslt {\lang1024 30}}}{\lang1024=20
\par 1.4.2.2.12\tab Effective Drive Internal Resistance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646155 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350035000000}}
}{\fldrslt {\lang1024 31}}}{\lang1024=20
\par 1.4.2.2.13\tab Equivalent Custom Wire Drive - ???\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646156 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350036000000}}
}{\fldrslt {\lang1024 32}}}{\lang1024=20
\par 1.4.2.2.14\tab Output Port Internal Lumped RC parasitic model\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646157 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350037000000}}}{\fldrslt {\lang1024 =
32}}}{\lang1024=20
\par 1.4.2.2.15\tab Output Port Distributed Hierarchical Boundary =
Parasitics (Impedance)\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646158 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350038000000}}}{\fldrslt {\lang1024 =
33}}}{\lang1024=20
\par 1.4.2.2.16\tab Unterminated (Open Circuit) Interface Output Port =
Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646159 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350039000000}}}{\fldrslt {\lang1024 =
33}}}{\lang1024=20
\par 1.4.2.2.17\tab Terminated (Loaded) Instance (Occurrence) Output =
Port Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc440646160 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360030000000}}}{\fldrslt {\lang1024 =
34}}}{\lang1024=20
\par 1.4.2.2.18\tab Distributed R-C Output Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646161 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360031000000}}}{\fldrslt {\lang1024 =
35}}}{\lang1024=20
\par 1.4.2.2.19\tab Distributed R-C-L Output Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646162 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360032000000}}}{\fldrslt {\lang1024 =
35}}}{\lang1024=20
\par 1.4.2.2.20\tab Distributed R-C-L-M Output Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646163 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360033000000}}}{\fldrslt {\lang1024 =
36}}}{\lang1024=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
}}\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\kerning28 =
\sect }\sectd =
\marglsxn1440\margrsxn2160\margtsxn1613\margbsxn1685\psz1\sbkcol\linex0\=
colsx0\titlepg\sectdefaultcl=20
{\*\bkmkstart clock}{\*\bkmkstart parasitics}{\*\bkmkstart =
_Toc422101856}{\*\bkmkstart _Toc440646101}{\*\bkmkend clock}{\*\bkmkend =
parasitics}{\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 1\tab}\pard\plain=20
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls38\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20 Design Constraints \endash Especially =
Timing Constraints Driving Synthesis
{\*\bkmkend _Toc440646101} {\*\bkmkend _Toc422101856}
\par {\*\bkmkstart _Toc440646102}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.1\tab}}\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls38\ilvl1\out=
linelevel1\adjustright \b\cgrid {(See ParasaticsDiscussion04sg)
{\*\bkmkend _Toc440646102}
\par {\*\bkmkstart _Toc440646103}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.2\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc440646103}
\par {\*\bkmkstart _Toc440646104}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.3\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc440646104}
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4\tab}\page {\*\bkmkstart _Toc440646105}Hierarchical Parasitic =
Boundary Conditions{\*\bkmkend _Toc440646105}=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {This =
section defines constraint terms for hierarchical parasitic boundary =
conditions. =20
\par Note that, when available and where applicable, the related term =
from the Ambit constraint strawman is also included for reference.
\par {\*\bkmkstart mark}{\*\bkmkstart _Toc432826548}{\*\bkmkstart =
_Toc434042497}{\*\bkmkstart _Toc434061598}{\*\bkmkstart =
_Toc440646106}{\*\bkmkend mark}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1\tab}}\pard\plain=20
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls42\ilvl2\outlinelevel2\adjustright \b\cgrid {Port General Parasitic =
Boundary Conditions{\*\bkmkend _Toc440646106}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
following parasitic constraint definitions apply to both input and =
output ports.}{\cs46\super \chftn {\footnote \pard\plain =
\s45\qj\sb120\widctlpar\adjustright \fs20\cgrid {\cs46\super \chftn }
{ Note: The Ambit }{constraint}{ strawman stated several port or =
boundary constraints from the point of view of applying to either input =
or output ports. }}}{
\par {\*\bkmkstart _Toc440646107}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Capacitance
{\*\bkmkend _Toc440646107}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the =
capacitance external to the cell, block or design=20
based on input and output loading from other ports and nets connected =
to the ports of the current module.
\par The total }{\cgrid0 external }{\cgrid0 capacitance at any port is =
the sum of the external port and net capacitances that the port is =
connected to in the design hierarchy. Note that this capacitance does =
not include any capacitance contribution of=20
the port itself or any contribution from the port and net lying behind =
the port inside the cell.
\par For an input port, the Port Capacitance refers to the capacitance =
contributed by all the ports of the drivers that may be connected to =
the external hierarchical net, and the capacitance of the other loads =
on the external hierarchical net.=20
\par For output ports, the port capacitance refers to the capacitance =
of all the external sinks, and/or }{\cgrid0 external }{\cgrid0 drivers, =
for the case of a multiply-driven net, that are connected to the =
external hierarchical net. This capacitance includes=20
capacitance contributions of other input ports and of any other =
external drivers connected to the hierarchical net.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or output ports of a cell or =
cell instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Capacitance of the connected net, =
its own capacitance, and the capacitances of the ports connected to the =
net
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell List of Identifier\cell \cell Identifies the ports on =
the target cell or cell instance=20
that will have the capacitance value.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell or =
cell instance\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell Name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10170\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Sum of the }{capacitance =
}{contributions of the ports and net of the external hierarchical =
network connected to the target port\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row {\*\bkmkstart =
_Toc440646108}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar
\jclisttab\tx1152\ls38\ilvl5\outlinelevel5\adjustright \i\fs22\cgrid =
{\cgrid0 Reference only: set_port_capacitance }{\fs20 =
(Ambit){\*\bkmkend _Toc440646108}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f18\cf1\cgrid0 Command}{\f18\cf1\cgrid0 : }{\f6\fs16\cf1\cgrid0 =
set_port_capacitance
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\b\f1\fs18\cgrid0 :}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance <capacitance> <port_list>
\par }{\b\cgrid0 Description: }{\cgrid0 The }{\f6\fs16\cgrid0 =
set_port_capacitance }{\cgrid0 command specifies the capacitance =
external to the design based on input and output loading from other =
ports and nets connected to the ports of the current module.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0 =
The capacitance at any port is the sum of the external port =
capacitances the port is connected to. For an input port the
port capacitance refers to the capacitance of all the ports of the =
driver that are connected to the net and the capacitance of the other =
loads on the net. For output ports, the port capacitance refers to the =
capacitance of all the external sinks, or exte
rnal drivers, for the case of multiply-driven net, that are connected =
to the net as well as the capacitance of the input port of any other =
external drivers
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Arguments: =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f19\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par port_list }{\i\f19\cgrid0 \emdash }{\f1\fs18\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
None
\par }{\b\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb240\widctlpar\adjustright {\b\cgrid0 Design Database: =
}{\cgrid0 None
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_current_module, set_port_capacitance_limit
\par }{\b\cgrid0 Examples: }{\cgrid0 This command sets a 3.2 =
capacitance on all output ports of the current module whose names match =
dbus at the start The unit of capacitance will be the same as the unit =
of capacitance used in the library.
\par }\pard \fi720\sb120\widctlpar\adjustright {\f2\cgrid0 =
set_port_capacitance 3.2 [find -port \endash output }{\f2\cf1\cgrid0 =
bus*]
\par {\*\bkmkstart _Toc440646109}{\listtext\pard\plain\s5 \b\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\cgrid0=20
Port Capacitance Limit{\*\bkmkend _Toc440646109}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the maximum =
value of the }{\fs18\cgrid0 capacitance}{\cgrid0 external to the =
target=20
port based on the sum of all the capacitance of all input =
}{\fs18\cgrid0 and output ports and net that are hierarchically =
connected to the target port of the target cell. This constraint =
}{\cgrid0 may be used to override global capacitance constraints.

\par This constraint may be specified on a cell interface =
(input}{\f18\cgrid0 and output) port of a design hierarchy, including =
}{\cgrid0 on a top }{\f18\cgrid0 level input and/or output port. This =
sets the constraint that the total capacitances (i.e.,
net or wire capacitance and port capacitance) of hierarchical nets =
attached to the ports in the port list do not exceed the specified =
maximum value of capacitance
. This constraint may be used to override the default port or net =
capacitance limit constraint that may be separately set by the =
}{\f6\fs16\cgrid0 Global_Capacitance_Limit constraint}{\f1\fs18\cgrid0 =
.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard =
\s30\li288\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright {\b =
Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or output ports of a cell or =
cell instance=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for =
capacitance loading of an input or output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target Port =
name or list\cell List of Identifier\cell The target port(s) must exist =
within target cell\cell=20
Identifies all the ports that are to have the port capacitance limit =
value\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell or cell instance\cell Identifier
\cell Cell must exist in the target design hierarchy\cell Name of the =
cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 \trbrdrb
\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
limit value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Maximum value of capacitance of the =
ports and net external to the target ports\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard=20
\qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646110}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference only: set_port_capacitance_limit }{(Ambit)}{\cgrid0 =
{\*\bkmkend _Toc440646110}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
{\b\f18\cgrid0 Command:}{\f18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit
\par }{\b\fs18\cgrid0 Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit <capacitance> <port_list>
\par }{\b\fs18\cgrid0 Description:}{\cgrid0 The }{\fs16\cgrid0 =
set_port_capacitance_limit }{\cgrid0 command specifies the limit on the =
}{\fs18\cgrid0 capacitance}{\cgrid0 (maximum value) external to the =
design based on input }{\fs18\cf1\cgrid0=20
and output loading from other ports and nets connected to the ports of =
the current module. }{\cf1\cgrid0 It is used to override design rule =
constraints set by the global attribute
\par }{\b\fs18\cgrid0 set_capacitance_limit:}{\cgrid0 These =
constraints can be specified on top }{\f18\cf1\cgrid0 level input and =
output ports. It sets the constraint that the total capacitances (i.e., =
wire capacitance a
nd pin capacitance) of nets attached to the ports in the port list do =
not exceed the specified capacitance limit. This command overrides the =
default limit set by the }{\f6\fs16\cf1\cgrid0 =
set_global_capacitance_limit }{\f18\cf1\cgrid0 command}{
\f1\fs18\cf1\cgrid0 .
\par }{\b\fs18\cgrid0 Arguments:}{\cgrid0 =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f19\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f19\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\fs18\cgrid0 Options:}{\cgri=
d0 None
\par }{\b\fs18\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb120\nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_fanout_load_limit, }{\f1\fs18\cf1\cgrid0 =
set_slew_limit, set_port_capacitance
, set_num_external_sources, set_num_external_sinks, do_derive_context, =
do_time_budget, set_global capacitance_limit
\par }{\b\cgrid0 Examples:}{\f1\cgrid0 }{\cgrid0 =
set_port_capacitance_limit 5.0 [find -port dbus*]
\par {\*\bkmkstart _Toc440646111}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Global Capacitance Limit{\*\bkmkend _Toc440646111}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Global Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the default =
maximum value of the }{\fs18\cgrid0 capacitance}{\cgrid0 is defined to =
exist external to the target port
}{\fs18\cgrid0 . }{\cgrid0=20
\par This constraint may be specified on a cell interface =
input}{\f18\cgrid0 or output port of a design hierarchy, including =
}{\cgrid0 on a top }{\f18\cgrid0 level input port. This defines the =
constraint of the default maximum capacitance=20
(i.e net or wire capacitance and port capacitance) of hierarchical =
network external to the target ports in the port list. This constraint =
may be overriden by defining a port or net capacitance limit =
constraints.}{\f1\fs18\cgrid0=20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for default =
maximum capacitance loading of an input or output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Default =
External }{Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell }{Default maximum }{value of =
capacitance of the ports and net external to the target ports\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646112}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls42\ilvl2\outlinelevel2\adjustright \b\cgrid {
Input Port Specific Parasitic Boundary Conditions{\*\bkmkend =
_Toc440646112}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
following constraint definitions are specific to input ports.
\par {\*\bkmkstart _Toc440646113}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls38\ilvl3\outlinelevel3\adjustright \b\cgrid {
Input Port External Environment Constraints{\*\bkmkend _Toc440646113}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortExternal}{\*\bkmkend InputPortExternal}
The following are descriptions and constraints found at the input ports =
of the external implementation or instance of block when it is used =
within a design hierarchy. That is, these constrai
nts describe or prescribe those properties of the environment =
surrounding the use of an input port of an instance of a block. These =
constraints are part of the characteristics of what may or should =
happen at or near the input port of an instance of a bloc
k when later signals propagate to the input port via the surrounding =
interconnect at the next level of the design hierarchy.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls30\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls30\adjustright \fs20\cgrid {
(Note: In CHDStd hierarchical representation, these input port external =
environment constraints are properties of an instance port (usage_port) =
of the block instance and comprise part of the block instance =
(usage_box) interface definition.)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc440646114}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Equivalent External Sources{\*\bkmkend _Toc440646114}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Equivalent External Sources
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies the number of ports =
that are or may be connected to
the target port and are able to drive it. The number is stated in =
terms of a typical strength driving port. }{\cgrid0 This number is =
factored into the wire capacitance and wire resistance estimation done =
for the net connected to the target port.}{

\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Cell Parasitics Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Hierarchical connectivity fanin
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell Restrictions\cel=
l Semantics\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the in
put port on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Cell identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10147\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number external ports\cell Float\cell \cell Number of =
equivalent ports\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row {\*\bkmkstart =
_Toc440646115}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar
\jclisttab\tx1008\ls38\ilvl4\outlinelevel4\adjustright \b\fs22\cgrid =
{Number External Sources (Ambit \endash =
num_external_sources){\*\bkmkend _Toc440646115}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Number External Sources
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
Specifies the number of actual external ports that are or may be =
connected to the target port of a cell or cell instance and are driving =
it. }{\cgrid0 This number is factored i
nto the wire capacitance and wire resistance estimation done for the =
net connected to the target port.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Hierarchical connectivity fan-in
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10147\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number external ports\cell Float\cell \cell Number of =
actual or potential ports external to the target port
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646116}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0 Reference only=20
\endash set_num_external_sources{\*\bkmkend _Toc440646116}(Ambit)
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f18\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_num_external_sources
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_num_external_sources =
<num_sources> <port_list>
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 Description: =
}{\cf1\cgrid0 The set_nu
m_external_sources command can be specified on top level input and =
output ports. This command sets the constraint that the number of =
external sources specified by the command are connected to the ports in =
the port list. This number is factored into the wi
re capacitance and wire resistance estimation done for the port nets =
using the wire load models.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f1\fs18\cf1\cgrid0 num_sources \emdash Number of external sources
\par }\pard \sb120\nowidctlpar\adjustright {\f1\fs18\cf1\cgrid0 =
port_list \emdash List of ports
\par }\pard\plain \s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid =
{\f0\cgrid0 Options:
\par Attributes:
\par Design Database:
\par Related Commands:
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\b\cf1\cgrid0 =
Examples:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs18\cf1\cgrid0 =
set_num_external_sinks
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs18\cf1\cgrid0 =
set_port_capacitance
\par do_derive_context
\par do_time_budget}{\f18\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646117}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Input Port External Wire Load{\*\bkmkend _Toc440646117}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {(Derived =
from the Ambit definition)
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Wire Load
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies the wire load model =
that will be applied to a net that is connected to the target input or =
output=20
interface port (e.g., top level port) of a cell when the cell is =
instantiated in a design. The }{\cgrid0 specified wire load model =
information is used for wire capacitance and resistance estimation. If =
more than one port with this port_wire
_load assertion is connected to the net, then the worst-case of all the =
wire load model assertions shall be used in=20
estimating the wire capacitance and resistance for the net. The Library =
Name identifies the library that contains the specified wire load model
data. If the library is not specified, then the default wire load =
model information for the target technology shall be used.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{None
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell \cell Identifies the port on the target cell =
or cell instance \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design =
hierarchy\cell name of the cell (if the top cell) or cell instance
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Wire load =
model name\cell Identifier\cell Optional\cell Name of the Wire load =
model that is to optionally be applied to the target input port\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10170\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Library name
\cell Identifier\cell Optional\cell Name of optional Library that =
contains the Wire load model. If the library is not identified, then =
the wire load model information of the technology shall be used.\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646118}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.3.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference only: set_port_wire_load{\*\bkmkend _Toc440646118}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Command:}{\f18\cgrid0 }{\cgrid0 set_port_wire_load
\par }\pard \widctlpar\adjustright {\b\cgrid0 Syntax:}{\f1\fs18\cgrid0 =
}{\cgrid0 set_port_wire_load ?-library <library_name>? <wire_load> =
}{\f6\fs16\cf1\cgrid0 <port_list>
\par }{\b\cgrid0 Description:}{\cgrid0 }{ }{\cgrid0 The =
set_port_wire_load command specifies the wire load for either =
}{\cf1\cgrid0=20
an input or output top level port of a design. The net connected to the =
port is associated with the specified wire load model, which is used =
for wire cap and resistance estimation. If a net i
s connected to more than one port with a set_port_wire_load assertion, =
then the worst wire load model is computed and used for the net. The =
library name indicates the location of the specified wire load model. =
If the library is not specified, then the wir
e load is located from the target technology (the default location).
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }{\b\cgrid0 Options:}{\cgrid0=20
\par }{\b\cgrid0 Attributes:}{\cgrid0=20
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_wire_load, =
set_num_external_sinks
\par }{\b\fs18\cf1\cgrid0 Examples:
\par {\*\bkmkstart _Toc440646119}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Input Port Wire Load=20
{\*\bkmkend _Toc440646119}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {See =
port_wire_load.
\par }\pard \sb120\nowidctlpar\adjustright {\f18\fs16\cf1\cgrid0=20
\par {\*\bkmkstart _Toc440646120}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls38\ilvl3\outlinelevel3\adjustright \b\cgrid {
Input Port Internal Implementation Constraints{\*\bkmkend =
_Toc440646120}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortInternal}{\*\bkmkend InputPortInternal}
The following are definitions and constraints found at the input ports =
of the internal definition or implementation of a block that will later =
be reused as a block instance in a design hierarchy (and as an =
occurrence in the unfolde
d design). That is, these definitions and constraints are those =
properties of an input port and possibly its associated interconnect =
found within a design definition of a design hierarchy. These =
constraints are part of the characteristics of what may o
r should happen at or near the input port when signals flow in through =
the input port to the rest of the block definition via the associated =
nearby interconnect.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls30\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls30\adjustright \fs20\cgrid {
(Note: In CHDStd hierarchical representation, these input port internal =
implementation constrai
nts are properties of an input port (proto_port) of the internal =
definition (proto_box) of a block (def_box). These input port =
properties comprise part of the block\rquote=20
s interface definition for one particular definition (aka view or VHDL =
architecture body) of the block.)
\par {\*\bkmkstart _Toc440646121}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Inter
nal Capacitance{\*\bkmkend _Toc440646121}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Internal Capacitance, Input Port Internal =
Capacitance, Output Port Internal Capacitance
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the =
capacitance }{\cgrid0 internal }{\cgrid0 to the cell, block or design=20
based on input and output loading from other ports and nets connected =
to the }{\cgrid0 target port }{\cgrid0 of the current module.
\par The total }{\cgrid0 internal }{\cgrid0 capacitance at any port is =
the sum of the }{\cgrid0 other internal }{\cgrid0 port and net =
capacitances that the }{\cgrid0 target }{\cgrid0 port is connected to =
in the design hierarchy.=20
Note that this capacitance does not include any capacitance =
contribution of the port itself or any contribution from the port and =
net }{\cgrid0 external to }{\cgrid0 the port }{\cgrid0 outside =
}{\cgrid0 the cell.
\par For an input port, the Port Capacitance refers to the capacitance =
contributed by all the ports of the drivers that may be connected to =
the }{\cgrid0 internal }{\cgrid0 hierarchical net, and the capacitance =
of the other loads on the }{\cgrid0 internal }{
\cgrid0 hierarchical net.=20
\par For output ports, the port capacitance refers to the capacitance =
of all the }{\cgrid0 internal }{\cgrid0 sinks, and/or }{\cgrid0 =
internal }{\cgrid0 drivers, for the case of a multiply-driven net, that =
are connected to the }{\cgrid0 internal }{\cgrid0=20
hierarchical net. This capacitance includes capacitance contributions =
of other input ports and of any other }{\cgrid0 internal }{\cgrid0 =
drivers connected to the hierarchical net.}{
\par }{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab }{Input or output ports of a cell =
or cell instance}{=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Capacitance of the connected net, =
and the capacitances of the }{other }{ports connected to the net}{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell List of Identifier\cell \cell Identifies the ports on =
the target cell or cell instance=20
that will have the capacitance value.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell or =
cell instance\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell Name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Sum of the capacitance contributions =
of the ports and net of the external hierarchical network connected to =
the target port\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\qj\sb120\widctlpar\adjustright {
\par }\pard \sb120\nowidctlpar\adjustright {\f18\fs16\cf1\cgrid0=20
\par {\*\bkmkstart _Toc440646122}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Input Port Internal Capacitance Limit{\*\bkmkend _Toc440646122}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the maximum =
value of the }{\fs18\cgrid0 capacitance}{\cgrid0 }{\cgrid0 internal =
}{\cgrid0 to the target=20
port based on the sum of all the capacitance of all input =
}{\fs18\cgrid0 and output ports and net that are hierarchically =
connected to the target port of the target cell. This constraint =
}{\cgrid0 may be used to override global capacitance constraints.

\par This constraint may be specified on a cell interface =
(input}{\f18\cgrid0 and output) port of a design hierarchy, including =
}{\cgrid0 on a top }{\f18\cgrid0 level input and/or output port. This =
sets the constraint that the total }{\f18\cgrid0 internal }{
\f18\cgrid0 capacitances (i.e., net or wire capacitance and port =
capacitance) of hierarchical nets attached to the ports in the port =
list do not exceed the specified maximum value of capacitance
. This constraint may be used to override the default port or net =
capacitance limit constraint that may be separately set by the =
}{\f6\fs16\cgrid0 Global_Capacitance_Limit constraint}{\f1\fs18\cgrid0 =
.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for =
capacitance loading of an input or output port}{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target Port =
name or list\cell List of Identifier\cell The target port(s) must exist =
within target cell\cell=20
Identifies all the ports that are to have the port capacitance limit =
value\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell or cell instance\cell Identifier
\cell Cell must exist in the target design hierarchy\cell Name of the =
cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 \trbrdrb
\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
limit value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Maximum value of capacitance of the =
ports and net }{internal }{to the target ports\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row=20
}\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646123}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Input port drive strength :{\*\bkmkend _Toc440646123} =20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Input port drive strength
\par }\pard\plain \qj\sb240\widctlpar\adjustright \fs20\cgrid {Semantic =
definition: Identifies the amount of transistor circuit output =
capability available to drive from some higher or lower level circuitry =
of the design hierarchy into an input port and on=20
into the net and ports connected to the target input port.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Drive capability of the ports =
external to the target cell or cell instance
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 \trbrdrb\brdrs\brdrw1=
0 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list of names\cell Identifier\cell Input or bi-directional =
port\cell Identifies th
e input port on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Drive Strength
\cell Float\cell \cell {\*\bkmkstart save}{\*\bkmkend save}\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt
\brdrs\brdrw30\brdrcf1 \trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par }\pard \sb120\nowidctlpar\adjustright {\f18\fs16\cf1\cgrid0=20
\par }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646124}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Effective Load Capacity{\*\bkmkend _Toc440646124}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646125}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.5\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Equivalent Load
{\*\bkmkend _Toc440646125}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646126}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.6\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Input Port Lumped RC parasitic model{\*\bkmkend _Toc440646126}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b Semantic =
definition:}{
The distributed parasitic effects of a net or netsegment are =
represented by a single lumped value of capacitance and resistance. =
Nominal, best-case, and worst-case RC value pa
irs may be specificed from which to calculate nominal, best-case, =
and/or worst-case net or netsegment delay, slew, and other related =
timing characteristics.
\par }{\b Type:}{\tab Parasitic
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To:}{\tab Hierarchical pins or primitive =
outputs
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On:\tab }{process: Coefficient=20
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By:}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646127}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.7\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Input Port Distributed Hierarchical Boundary Parasitics =
(Impedance){\*\bkmkend _Toc440646127}
\par }\pard\plain \widctlpar\adjustright \fs20\cgrid {This section =
defines the distributed R-C, R-L-C, and R-L-C-M parasitic boundary =
conditions for initial estimation of instantiating blocks, cells, and =
macros, and for later backannotated actual parasitics.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {The =
approach described in this section currently is being examined for =
applicability to fully accurate hierarchical net timing stored within =
the folded (instance) desi
gn hierarchy. (I recently found published information that this =
approach is in used within a major EDA supplier.) =20
\par The analysis and work todate indicates that at least of large =
number of nets may be accurately calculated from the below hierarchical =
two po
rt parasitic boundary conditions if the timing is then captured =
arc-wise in a timing view which also have both internal and interface =
timing arcs. An additional instance-port incremental timing offset =
value is required at the \lquote edge\rquote=20
of the block-instance\rquote s interface timing view as part of =
representing the information required for an full instantiation of a =
hierarchical net parasitic model.
\par {\*\bkmkstart _Toc440646128}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.8\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Unterminated (Open Circuit) Interface Input Port Parasitic (impedance) =
model{\*\bkmkend _Toc440646128}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {The =
Unterminated interface port parasitics model encapsulates the effects =
of the interface nets behind the port.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646129}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.9\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Terminated (Loaded) Instance (Occurrence) Input Port Parasitic =
(impedance) model{\*\bkmkend _Toc440646129}=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {The =
terminated instance port parasitics model encapsulates the incremental =
effects of the interface nets as (potentiall
y) loaded by the parasitics of the nets at the next level of the design =
hierarchy.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646130}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.10\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Distributed R-C Input Port Parasitics{\*\bkmkend _Toc440646130}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdr=
w10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646131}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.11\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Distributed R-C-L Input Port Parasitics{\*\bkmkend _Toc440646131}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Cell must
exist in the target design hierarchy\cell name of the cell (if the top =
cell) or cell instance\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell=20
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646132}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3.12\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Distributed R-C-L-M Input Port Parasitics{\*\bkmkend _Toc440646132}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par=20
\par=20
\par {\*\bkmkstart _Toc440646133}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls38\ilvl2\outlinelevel2\adjustright \b\cgrid {
Output Port Parasitic Boundary Conditions{\*\bkmkend _Toc440646133}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc440646134}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls38\ilvl3\outlinelevel3\adjustright \b\cgrid {
Output port External Environment Constraints{\*\bkmkend _Toc440646134}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart OutputPortExternal}{\*\bkmkend OutputPortExternal}The =
following are descripti
ons and constraints found at the output ports in an external =
implementation of a cell or block or for an instance of a block =
definition when the block is used within a design hierarchy. That is, =
these constraints describe or prescribe those properties of
=20
the environment surrounding the use of an output port of an instance of =
a block. These constraints are part of the characteristics of what may =
or should happen at or near the output port of an instance of a block =
when, later, signals propagate out throug
h the output port to the interconnect of the next higher level part of =
the design hierarchy.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls30\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls30\adjustright \fs20\cgrid {
(Note: In CHDStd hierarchical representation, these output port =
external environment constraints are properties of an instance port =
(usage_port) of the block instance and comprise part of the block =
instance (usage_box) interface definition.)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc440646135}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port Wire Load (Ambit){\*\bkmkend _Toc440646135}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {See =
set_port_wire_load.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Cell=20
must exist in the target design hierarchy\cell name of the cell (if the =
top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell=20
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646136}{\listtext\pard\plain\s5 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\fs20 Fanout
{\*\bkmkend _Toc440646136}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {Fanout: =
The number of separate ports that can be driven or the effective number =
of loads that can be driven looking into a external port.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646137}{\listtext\pard\plain\s5 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\fs20 Fanout Drive
{\*\bkmkend _Toc440646137}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain \s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390=
\adjustright \fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary =
Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646138}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Fanout Load (Ambit)
{\*\bkmkend _Toc440646138}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par }\pard \sb120\nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Ambit =
Command:}{\f18\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 set_fanout_load
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 set_fanout_load <load> <port_list>
\par }{\b\fs18\cf1\cgrid0 Ambit Description:}{\i\fs18\cgrid0 }{\cgrid0 =
The }{\f6\fs16\cgrid0 set_fanout_load }{\cgrid0=20
command is used to specify the fanout load on the ports of a cell. =
While port capacitance affects timing analysis, fanout loads are used =
to enforce the design rule checks.
\par }{\b\fs18\cf1\cgrid0 DCWG Description:}{\cgrid0 }{\f6\fs16\cgrid0 =
fanout_load: }{\cgrid0=20
Specifies the expected or budgeted fanout load on the ports of a cell =
when the cell is instantiated. While port capacitance affects timing =
analysis, fanout loads are used during planning the loading of
a cell, and later to enforce the design rule checks of the application =
or use a cell.
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }\pard \fi720\sb120\widctlpar\adjustright {\cgrid0 Ambit =
Arguments:
\par }\pard \fi720\li720\sb120\widctlpar\adjustright {\cgrid0 =
Load;}{\i\f19\cgrid0 }{\f1\fs18\cgrid0 Total fanout load external to =
the cell.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f19\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 List of ports.}{\f1\fs18\cgrid0=20
\par }\pard \fi720\sb120\widctlpar\adjustright {\cgrid0 DCWG =
Load;}{\i\f19\cgrid0 }{\f1\fs18\cgrid0 Total fanout load external to =
the cell.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f19\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 List of ports.}{\f1\fs18\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
}{\f6\fs16\cgrid0 None
\par }\pard \widctlpar\adjustright {\b\cgrid0 Attributes:}{\cgrid0 =
fanout_load_limit
\par }{\b\cgrid0 Design Database:}{\cgrid0 =20
\par }\pard \nowidctlpar\adjustright {\b Related =
Commands}{\b\f1\fs18\cf1\cgrid0 :}{\f1\fs18\cf1\cgrid0 =
set_current_module
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646139}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.5\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Fanout Load Limit (Ambit){\*\bkmkend _Toc440646139}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646140}{\listtext\pard\plain\s5 \b\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.6\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\cgrid0=20
set_fanout_load_limit{\*\bkmkend _Toc440646140}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\fs18\cf1\cgrid0 Command:}{\f18\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Syntax:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit <load port_list>
\par }\pard \sb120\nowidctlpar\adjustright {\b\cf1\cgrid0 =
Description:}{\cf1\cgrid0 The set_fanout_load_
limit command is used to specify the fanout load limit (maximum value) =
on the ports of a cell. While port capacitance affects timing analysis, =
fanout loads are used to enforce the design rule checks. The design =
rule requirement of a maximum fanout load v
alue is set using the global attribute fanout_load_limit. =20
\par }{\f18\cf1\cgrid0 This command overrides the default fanout load =
limit on specific ports set by the global attribute =
}{\f6\fs16\cf1\cgrid0 fanout_load_limit}{\f18\cf1\cgrid0 .
\par }{\b\fs18\cf1\cgrid0 Arguments:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 load }{\i\f19\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 Fanout load limit on the ports.
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f19\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Options:}{\f1\fs18\cf1\cgrid0 None
\par }{\b\fs18\cf1\cgrid0 Attributes:}{\f1\fs18\cf1\cgrid0 =
fanout_load_limit
\par }{\b\fs18\cf1\cgrid0 Design Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_current_module, =
set_fanout_load
\par }{\b\fs18\cf1\cgrid0 Examples:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_fanout_load_limit 4 [find -port -output =
data*]}{\f18\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646141}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.7\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port External Fanout m <redundant?>{\*\bkmkend _Toc440646141}
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Identifies the number of =
effective loads (transistor circuits) lying behind an output port.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx4500\clvertalt\clbrdrt\br=
drs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646142}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls38\ilvl3\outlinelevel3\adjustright \b\cgrid {
Output Port Internal Implementation Constraints{\*\bkmkend =
_Toc440646142}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart OutputPortInternal}{\*\bkmkend OutputPortInternal}The =
following ar
e definitions and constraints found at the output ports of the internal =
definition or implementation of a block that will later be reused as a =
block instance in a design hierarchy (and as an occurrence in the =
unfolded design). That is, these definitions=20
a
nd constraints are those properties of an output port and possibly its =
associated local interconnect found within a design definition of a =
design hierarchy. These constraints are part of the characteristics of =
what may or should happen at or near the ou
tput port when signals flow to the output port via the surrounding =
interconnect of the internal or local design definition.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls30\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls30\adjustright \fs20\cgrid {
(Note: In CHDStd hierarchical representation, these output port =
internal implementation constraints are properties of an output port=20
(proto_port) of the internal definition (proto_box) of a block =
(def_box). These output port properties comprise part of the =
block\rquote s interface definition for one particular definition (aka =
view or VHDL architecture body) of the block.)=20
\par {\*\bkmkstart _Toc440646143}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Output Port Equivale
nt Custom Wire Load{\*\bkmkend _Toc440646143}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
While wire load models normally apply to the target net, during that =
portion of the design flow where wire load parasitics are being used, =
we will need also to encapsulate and store the effective amount of =
wireload model that is present
at the hierarchical port or port instance.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646144}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Equivalent Custom Wire Load Mode (Ambit){\*\bkmkend _Toc440646144}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646145}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Specified Wire Load Model (Ambit){\*\bkmkend _Toc440646145}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646146}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port Drive Capability{\*\bkmkend _Toc440646146}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain \s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390=
\adjustright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646147}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.5\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Cell (Block) Drive (Ambit){\*\bkmkend _Toc440646147}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646148}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.6\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Drive resistance (Ambit){\*\bkmkend _Toc440646148}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\b=
rdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Cell must exist=20
in the target design hierarchy\cell name of the cell (if the top cell) =
or cell instance\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell=20
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646149}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.6.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
set_drive_resistance{\*\bkmkend _Toc440646149}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f18\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 set_drive_resistance
\par }{\b\cf1\cgrid0 Syntax:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_drive_resistance ?-rise | -fall? ?-early | =
-late? value
\par port_list
\par }{\b\cf1\cgrid0 Description: }{\cf1\cgrid0 The set_
drive_resistance command is a simpler version of the set_drive_cell =
command and can be used in many situations where the drive resistance =
can be specified. It is only used for timing analysis. It does not =
affect the electrical properties of the design. It
is used to specify the drive resistance of a cell. It computes an =
offset to the arrival time of an input and also changes the slew time =
used to compute the delay of the cell on the sink of the net.
\par The arrival time at the input port is modified by adding t
he RC constant to the specified arrival time at the input port. The RC =
constant is the capacitance(C) seen at the input port multiplied by the =
drive resistance (R). The RC value is used as the slew value for the =
delay calculation of the next cell. This co
mmand overrides the set_drive_cell command per port if it is the last =
command applied. Also, if set_drive_resistance is set for a port, =
set_slew_time is ignored for that port.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 value }{\i\f19\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 Resistance value.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f19\cf1\cgrid0 \emdash =
}{\f18\cf1\cgrid0 List of ports for which drive resistance is =
specified.
\par }{\b\f1\fs18\cf1\cgrid0 Options: }{\f1\fs18\cf1\cgrid0 =
-}{\f6\fs16\cf1\cgrid0 rise \emdash }{\f1\fs18\cf1\cgrid0 Specifies =
that the drive resistance is applicable to only the rising edge =
transition at the input port.
\par -}{\f6\fs16\cf1\cgrid0 fall \emdash }{\f1\fs18\cf1\cgrid0 =
Specifies that the resistance is applicable only to the falling edge =
transition at the input port. If either }{\f6\fs16\cf1\cgrid0 rise =
}{\f1\fs18\cf1\cgrid0 nor }{\f6\fs16\cf1\cgrid0 fall }{
\f1\fs18\cf1\cgrid0 options are specified then the resistance is =
applied to both transitions at the input port.
\par -}{\f6\fs16\cf1\cgrid0 early \emdash }{\f1\fs18\cf1\cgrid0 =
Specifies that the drive resistance should be applied to the early =
arrival time (hold time) for timing analysis.
\par }{\f18\cf1\cgrid0 -}{\f6\fs16\cf1\cgrid0 late \emdash =
}{\f1\fs18\cf1\cgrid0 Specifies that the drive resistance should be =
applied to the late arrival time (setup time) for timing =
analysis}{\f18\cf1\cgrid0 .
\par }{\f1\fs18\cf1\cgrid0 Attributes
\par }{\b\f1\fs18\cf1\cgrid0 Design Database: }{\f1\fs18\cf1\cgrid0=20
\par }{\b\f1\fs18\cf1\cgrid0 Related Commands: }{\f1\fs18\cf1\cgrid0 =
set_drive_cell
\par set_slew_time
\par }{\b\f1\fs18\cf1\cgrid0 Examples: }{\f6\fs16\cf1\cgrid0 =
set_drive_resistance=20
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
[expr 3 * [get_cell_drive -cell IV \endash pin A] ] [-input -port * =
]}{\f18\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646150}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.7\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Available Drive
{\*\bkmkend _Toc440646150}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par }{\b\i Drive Strength \endash cell(s) input ports.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition:=20
\par }\pard\plain \qj\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc440646151}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.8\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output port Drive Strength:{\*\bkmkend _Toc440646151} =20
\par }\pard\plain \qj\widctlpar\adjustright \fs20\cgrid {Identifies the =
amount of transistor circuit output capability available to drive out =
through an output port to some higher or lower level circuitry.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646152}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.9\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port Internal Capacitance{\*\bkmkend _Toc440646152}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646153}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.10\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port Internal Capacitance Limit{\*\bkmkend _Toc440646153}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input port on the target cell or cell i
nstance \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target cell \cell Identifier\cell Cell must exist in the =
target design hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par }\pard \sb120\widctlpar\adjustright {
\par }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646154}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.11\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Effective Drive Internal Capacitance{\*\bkmkend _Toc440646154}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input port on the
target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design =
hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646155}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.12\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Effective Drive Internal Resistance{\*\bkmkend _Toc440646155}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
t
he input port on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc440646156}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.13\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Equivalent Custom Wire Drive - ???{\*\bkmkend _Toc440646156}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646157}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.14\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port Internal Lumped RC parasitic model{\*\bkmkend =
_Toc440646157}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b Semantic =
definition:}{
The distributed parasitic effects of a net or netsegment are =
represented by a single lumped value of capacitance and resistance. =
Nominal, best-case, and worst-case RC value pairs may be specificed =
from which to calculate nom
inal, best-case, and/or worst-case net or netsegment delay, slew, and =
other related timing characteristics.
\par }{\b Type:}{\tab Parasitic
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To:}{\tab Hierarchical pins or primitive =
outputs
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On:\tab }{process: Coefficient=20
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By:}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell Restri
ctions\cell Semantics\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\trowd \trgaph108\trleft450 \clvertalt\cltxlrtb =
\cellx2250\clvertalt\cltxlrtb \cellx4500\clvertalt\cltxlrtb =
\cellx6894\clvertalt\cltxlrtb \cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdr=
w30\brdrcf1 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646158}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.15\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Output Port Distributed Hierarchical Boundary Parasitics =
(Impedance){\*\bkmkend _Toc440646158}
\par }\pard\plain \widctlpar\adjustright \fs20\cgrid {This section =
defines the distributed R-C, R-L-C, and R-L-C-M parasitic boundary =
conditions for initial estimation of instantiating blocks, cells, and =
macros, and for later backannotated actual parasitics.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {
The approach described in this section currently is being examined for =
applicability to fully accurate hierarchical net timing stored within =
the folded (instance) design hierarchy. (I recently found published =
inform
ation that this approach is in used within a major EDA supplier.) =20
\par The analysis and work todate indicates that at least of large =
number of nets may be accurately calculated from the below hierarchical =
two port parasitic boundary conditions if the timing i
s then captured arc-wise in a timing view which also have both internal =
and interface timing arcs. An additional instance-port incremental =
timing offset value is required at the \lquote edge\rquote of the =
block-instance\rquote=20
s interface timing view as part of representing the information =
required for an full instantiation of a hierarchical net parasitic =
model.
\par {\*\bkmkstart _Toc440646159}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.16\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Unterminated (Open Circuit) Interface Output Port Parasitic (impedance) =
model{\*\bkmkend _Toc440646159}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {The =
Unterminated interface port parasitics model encapsulates the effects =
of the interface nets behind the port.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646160}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.17\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Terminated (Loaded) Instance (Occurrence) Output Port Parasitic =
(impedance) model{\*\bkmkend _Toc440646160}=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {The =
terminated instance port parasitics model encapsulates the incremental =
effects of the interface nets as (potentially) loaded by the parasitics =
of the nets at the
next level of the design hierarchy.
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646161}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.18\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Distributed R-C Output Port Parasitics{\*\bkmkend _Toc440646161}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646162}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.19\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Distributed R-C-L Output Port Parasitics{\*\bkmkend _Toc440646162}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646163}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.20\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Distributed R-C-L-M Output Port Parasitics{\*\bkmkend =
_Toc432826548}{\*\bkmkend _Toc434042497}{\*\bkmkend =
_Toc434061598}{\*\bkmkend _Toc440646163}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par }}

--Boundary_(ID_boNMOLyIxiW0Ryoi4jyDqg)--

Next message: Vassilios Gerousis: "DC-WG: Voting On Cadence Proposal"
Previous message: David Barton: "DC-WG: DCDL and the SLDL constraint language"