DC-WG: RE: Version 8 of the DCWG boundary parasitic constraints

Steve.Grout@sematech.org
Tue, 16 Feb 1999 11:14:34 -0600

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The attached is the now-almost complete Version 8 draft of the boundary
parasitic constraints for the DCWG synthesis constraint.
- Not yet completely drafted are definitions for drive cell,
drive resistance and drive capacitance - These will be defined
and completed just after today's telcon, working from the
definitions within the AMBIT strawman.

This edition reflects the recent joint discussion with Greg
Schulte on the underlying computational and usage model for
constraints and related assertions, especially as used within
the AMBIT synthesis constraint strawman.

I will add the remaining 3 term definitions and submit it to the
reflector as version 9 later today.

--Steve Grout

Attachment: Parasitics08sg.rtf

--Boundary_(ID_XjSKs1Lp4MLgH0cHQ2SwYw)
Content-type: application/rtf; name=Parasitics08sg.rtf
Content-disposition: attachment; filename=Parasitics08sg.rtf
Content-transfer-encoding: quoted-printable
Content-Location: ATT-0-57EE2E07AEC5D211A9FC0001FA7EC64E-P ACAD2%7E1.RTF

{\rtf1\ansi\ansicpg1252\uc1 =
\deff0\deflang1033\deflangfe1033{\fonttbl{\f0\froman\fcharset0\fprq2{\*\=
panose 02020603050405020304}Times New =
Roman;}{\f1\fswiss\fcharset0\fprq2{\*\panose =
020b0604020202020204}Arial;}
{\f2\fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier =
New;}{\f3\froman\fcharset2\fprq2{\*\panose =
05050102010706020507}Symbol;}{\f4\froman\fcharset0\fprq2{\*\panose =
02020603050405020304}Times;}
{\f5\fswiss\fcharset0\fprq2{\*\panose =
020b0604020202020204}Helvetica;}{\f6\fmodern\fcharset0\fprq1{\*\panose =
00000000000000000000}Courier;}{\f7\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Geneva;}
{\f8\froman\fcharset0\fprq2{\*\panose 00000000000000000000}Tms =
Rmn{\*\falt Times New Roman};}{\f9\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Helv;}{\f10\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}MS Serif;}
{\f11\fswiss\fcharset0\fprq2{\*\panose 00000000000000000000}MS Sans =
Serif;}{\f12\froman\fcharset0\fprq2{\*\panose 00000000000000000000}New =
York;}{\f13\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}System;}
{\f14\fnil\fcharset2\fprq2{\*\panose =
05000000000000000000}Wingdings;}{\f15\fswiss\fcharset0\fprq2{\*\panose =
020b0604030504040204}Tahoma;}{\f16\fswiss\fcharset0\fprq2{\*\panose =
020b0a04020102020204}Arial Black;}
{\f17\fswiss\fcharset0\fprq2{\*\panose 020b0506020202030204}Arial =
Narrow;}{\f18\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}Palatino;}{\f19\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}NewCenturySchlbk;}
{\f20\froman\fcharset0\fprq0{\*\panose =
00000000000000000000}Times-Roman;}{\f21\froman\fcharset0\fprq0{\*\panose=
=
00000000000000000000}Times-Italic;}{\f22\fswiss\fcharset0\fprq2{\*\panos=
e 00000000000000000000}AvantGarde;}
{\f23\froman\fcharset0\fprq2{\*\panose 00000000000000000000}ITC =
Bookman;}{\f24\fswiss\fcharset0\fprq2{\*\panose =
00000000000000000000}Helvetica-Condensed;}{\f25\fswiss\fcharset0\fprq2{\=
*\panose 00000000000000000000}Helvetica-Narrow;}
{\f26\froman\fcharset0\fprq2{\*\panose =
00000000000000000000}ZapfChancery;}{\f27\fdecor\fcharset2\fprq2{\*\panos=
e =
00000000000000000000}ZapfDingbats;}{\f28\fnil\fcharset2\fprq2{\*\panose =
00000000000000000000}Marlett;}
{\f29\fmodern\fcharset0\fprq1{\*\panose 020b0609040504020204}Lucida =
Console;}{\f30\fswiss\fcharset0\fprq2{\*\panose =
020b0602030504020204}Lucida Sans =
Unicode;}{\f31\froman\fcharset0\fprq2{\*\panose =
02040602050305030304}Book Antiqua;}
{\f32\fnil\fcharset2\fprq2{\*\panose 01010601010101010101}Monotype =
Sorts;}{\f33\froman\fcharset0\fprq2{\*\panose =
02050604050505020204}Bookman Old =
Style;}{\f34\fswiss\fcharset0\fprq2{\*\panose =
020b0502020202020204}Century Gothic;}
{\f35\fscript\fcharset0\fprq2{\*\panose 03010101010201010101}Monotype =
Corsiva;}{\f36\froman\fcharset0\fprq2{\*\panose =
02040604050505020304}Century =
Schoolbook;}{\f37\froman\fcharset2\fprq2{\*\panose =
05050102010205020202}MT Extra;}
{\f38\fdecor\fcharset0\fprq2{\*\panose =
04020705040a02060702}Algerian;}{\f39\fswiss\fcharset0\fprq2{\*\panose =
020f0704030504030204}Arial Rounded MT =
Bold;}{\f40\fdecor\fcharset0\fprq2{\*\panose =
04030b070d0b02020403}Braggadocio;}
{\f41\fswiss\fcharset0\fprq2{\*\panose 020b0903060703020204}Britannic =
Bold;}{\f42\fscript\fcharset0\fprq2{\*\panose =
03060802040406070304}Brush Script =
MT;}{\f43\fdecor\fcharset0\fprq2{\*\panose 04020805060202030203}Colonna =
MT;}
{\f44\fdecor\fcharset0\fprq2{\*\panose =
04020505020e03040504}Desdemona;}{\f45\froman\fcharset0\fprq2{\*\panose =
0204060206030a020304}Footlight MT =
Light;}{\f46\fswiss\fcharset0\fprq2{\*\panose =
020b0806030902050204}Impact;}
{\f47\fdecor\fcharset0\fprq2{\*\panose 040307050d0c02020703}Kino =
MT;}{\f48\froman\fcharset0\fprq2{\*\panose 020a0a07050505020404}Wide =
Latin;}{\f49\fscript\fcharset0\fprq2{\*\panose =
03020802060602070202}Matura MT Script Capitals;}
{\f50\fdecor\fcharset0\fprq2{\*\panose =
040506030a0602020202}Playbill;}{\f51\froman\fcharset0\fprq2{\*\panose =
00050102010706020507}Map =
Symbols;}{\f52\froman\fcharset0\fprq2{\*\panose =
02020404030301010803}Garamond;}
{\f53\fscript\fcharset0\fprq2{\*\panose 030f0702030302020204}Comic Sans =
MS;}{\f54\fswiss\fcharset0\fprq2{\*\panose =
020b0604030504040204}Verdana;}{\f55\froman\fcharset2\fprq2{\*\panose =
05030102010509060703}Webdings;}
{\f56\froman\fcharset0\fprq2{\*\panose =
02040502050405020303}Georgia;}{\f57\fswiss\fcharset0\fprq2{\*\panose =
020b0603020202020204}Trebuchet =
MS;}{\f58\fmodern\fcharset0\fprq2{\*\panose =
020b0509000000000004}Monotype.com;}
{\f59\froman\fcharset0\fprq2{\*\panose 02040503050201020203}Minion =
Web;}{\f60\fnil\fcharset2\fprq2{\*\panose 05000000000000000000}MS =
Outlook;}{\f61\fswiss\fcharset0\fprq2{\*\panose =
020e0602030304020304}Albertus Medium;}
{\f62\fswiss\fcharset0\fprq2{\*\panose 020e0802040304020204}Albertus =
Extra Bold;}{\f63\fswiss\fcharset0\fprq2{\*\panose =
020b0603020204030204}Antique =
Olive;}{\f64\fswiss\fcharset0\fprq2{\*\panose 020b0502050508020304}CG =
Omega;}
{\f65\froman\fcharset0\fprq2{\*\panose 02020603050405020304}CG =
Times;}{\f66\froman\fcharset0\fprq2{\*\panose =
02040706040705040204}Clarendon =
Condensed;}{\f67\fscript\fcharset0\fprq2{\*\panose =
03030502040406070605}Coronet;}
{\f68\fmodern\fcharset0\fprq1{\*\panose 020b0409020202030204}Letter =
Gothic;}{\f69\fscript\fcharset0\fprq2{\*\panose =
03020702040402020504}Marigold;}{\f70\fswiss\fcharset0\fprq2{\*\panose =
020b0603020202030204}Univers;}
{\f71\fswiss\fcharset0\fprq2{\*\panose 020b0606020202060204}Univers =
Condensed;}{\f72\fswiss\fcharset0\fprq2{\*\panose =
020b0a04020102020204}Arial MT =
Black;}{\f73\fscript\fcharset0\fprq2{\*\panose =
03060802030402020204}Benguiat Frisky;}
{\f74\fdecor\fcharset0\fprq2{\*\panose =
04020905020d02060204}Bertram;}{\f75\fdecor\fcharset0\fprq2{\*\panose =
040c09040503070d0203}Challenge Extra =
Bold;}{\f76\fswiss\fcharset0\fprq2{\*\panose =
020f0804020102020204}Glowworm;}
{\f77\fscript\fcharset0\fprq2{\*\panose 03020402050402020203}Graphite =
Light;}{\f78\fscript\fcharset0\fprq2{\*\panose =
03010604040201010104}Lucida =
Casual;}{\f79\fnil\fcharset2\fprq2{\*\panose =
05010101010101010101}Milestones;}
{\f80\fscript\fcharset0\fprq2{\*\panose =
03020902050305070206}Nadianne;}{\f81\fnil\fcharset0\fprq2{\*\panose =
02010502050601010104}Old =
English;}{\f82\fdecor\fcharset0\fprq2{\*\panose =
040103030504070e0101}Party;}
{\f83\froman\fcharset0\fprq2{\*\panose 02070a04080905020204}Poster =
Bodoni;}{\f84\froman\fcharset0\fprq2{\*\panose =
02070402040307030201}Pompeii =
Capitals;}{\f85\fscript\fcharset0\fprq2{\*\panose =
03030602040407090b05}Signet Roundhand;}
{\f86\fswiss\fcharset0\fprq2{\*\panose 020f0706050301020404}Theatre =
Antoine;}{\f87\fdecor\fcharset0\fprq2{\*\panose =
04050602080702020203}Onyx;}{\f88\fnil\fcharset0\fprq2{\*\panose =
00000000000000000000}PG Text;}
{\f89\fnil\fcharset0\fprq2{\*\panose 00000000000000000000}PGMusic =
F;}{\f90\fswiss\fcharset0\fprq2{\*\panose 020b7200000000000000}PG Music =
Font;}{\f91\froman\fcharset0\fprq0{\*\panose =
00000000000000000000}Times-Bold;}
{\f92\froman\fcharset0\fprq2{\*\panose 00000000000000000000}Times =
Roman{\*\falt Times New Roman};}{\f93\fswiss\fcharset0\fprq2{\*\panose =
020be200000000000000}AHD Symbol =
Sans;}{\f94\froman\fcharset0\fprq2{\*\panose 02027200000000000000}AHD =
Symbol;}
{\f95\froman\fcharset0\fprq2{\*\panose 02040603050505030304}Calisto =
MT;}{\f96\fswiss\fcharset0\fprq2{\*\panose =
020e0705020206020404}Copperplate Gothic =
Bold;}{\f97\fswiss\fcharset0\fprq2{\*\panose =
020e0507020206020404}Copperplate Gothic Light;}
{\f98\fdecor\fcharset0\fprq2{\*\panose 04040404050702020202}Curlz =
MT;}{\f99\froman\fcharset0\fprq2{\*\panose =
02020904090505020303}Elephant;}{\f100\froman\fcharset0\fprq2{\*\panose =
02090707080505020304}Engravers MT;}
{\f101\fswiss\fcharset0\fprq2{\*\panose 020b0907030504020204}Eras Bold =
ITC;}{\f102\fswiss\fcharset0\fprq2{\*\panose 020b0805030504020804}Eras =
Demi ITC;}{\f103\fswiss\fcharset0\fprq2{\*\panose =
020b0402030504020804}Eras Light ITC;}
{\f104\fswiss\fcharset0\fprq2{\*\panose 020b0602030504020804}Eras =
Medium ITC;}{\f105\fdecor\fcharset0\fprq2{\*\panose =
04060505060202020a04}Felix =
Titling;}{\f106\fscript\fcharset0\fprq2{\*\panose =
03060902040502070203}Forte;}
{\f107\fswiss\fcharset0\fprq2{\*\panose 020b0503020102020204}Franklin =
Gothic Book;}{\f108\fswiss\fcharset0\fprq2{\*\panose =
020b0703020102020204}Franklin Gothic =
Demi;}{\f109\fswiss\fcharset0\fprq2{\*\panose =
020b0706030402020204}Franklin Gothic Demi Cond;}
{\f110\fswiss\fcharset0\fprq2{\*\panose 020b0903020102020204}Franklin =
Gothic Heavy;}{\f111\fswiss\fcharset0\fprq2{\*\panose =
020b0603020102020204}Franklin Gothic Medium;}
{\f112\fswiss\fcharset0\fprq2{\*\panose 020b0606030402020204}Franklin =
Gothic Medium Cond;}{\f113\fscript\fcharset0\fprq2{\*\panose =
03020402040607040605}French Script =
MT;}{\f114\fswiss\fcharset0\fprq2{\*\panose 020b0502020104020203}Gill =
Sans MT;}
{\f115\fswiss\fcharset0\fprq2{\*\panose 020b0506020104020203}Gill Sans =
MT Condensed;}{\f116\fswiss\fcharset0\fprq2{\*\panose =
020b0a06020104020203}Gill Sans Ultra Bold Condensed;}
{\f117\fswiss\fcharset0\fprq2{\*\panose 020b0a02020104020203}Gill Sans =
Ultra Bold;}{\f118\froman\fcharset0\fprq2{\*\panose =
02030808020601010101}Gloucester MT Extra Condensed;}
{\f119\fswiss\fcharset0\fprq2{\*\panose 020b0902020104020203}Gill Sans =
MT Ext Condensed Bold;}{\f120\froman\fcharset0\fprq2{\*\panose =
02020502050305020303}Goudy Old =
Style;}{\f121\fswiss\fcharset0\fprq2{\*\panose =
020b0706040902060204}Haettenschweiler;}
{\f122\fdecor\fcharset0\fprq2{\*\panose 04020605060303030202}Imprint MT =
Shadow;}{\f123\fswiss\fcharset0\fprq2{\*\panose =
020b0602030504020204}Lucida =
Sans;}{\f124\fmodern\fcharset0\fprq1{\*\panose =
020b0509030504030204}Lucida Sans Typewriter;}
{\f125\fswiss\fcharset0\fprq2{\*\panose 020e0502030308020204}Maiandra =
GD;}{\f126\fmodern\fcharset0\fprq2{\*\panose 02010509020102010303}OCR A =
Extended;}{\f127\fscript\fcharset0\fprq2{\*\panose =
030303020206070c0b05}Palace Script MT;}
{\f128\froman\fcharset0\fprq2{\*\panose 02020502060505020804}Perpetua =
Titling MT;}{\f129\froman\fcharset0\fprq2{\*\panose =
02020502060401020303}Perpetua;}{\f130\fscript\fcharset0\fprq2{\*\panose =
03070502040507070304}Rage Italic;}
{\f131\froman\fcharset0\fprq2{\*\panose 02060603050405020104}Rockwell =
Condensed;}{\f132\froman\fcharset0\fprq2{\*\panose =
02060603020205020403}Rockwell;}{\f133\froman\fcharset0\fprq2{\*\panose =
02060903040505020403}Rockwell Extra Bold;}
{\f134\fscript\fcharset0\fprq2{\*\panose 03040602040607080904}Script MT =
Bold;}{\f135\fswiss\fcharset0\fprq2{\*\panose 020b0602020104020603}Tw =
Cen MT;}{\f136\fswiss\fcharset0\fprq2{\*\panose 020b0606020104020203}Tw =
Cen MT Condensed;}
{\f137\fswiss\fcharset0\fprq2{\*\panose 020b0803020000000004}Tw Cen MT =
Condensed Extra Bold;}{\f138\fswiss\fcharset186\fprq2{\*\panose =
00000000000000000000}Franklin Gothic Demi Cond Balti;}
{\f139\fswiss\fcharset161\fprq2{\*\panose 00000000000000000000}Franklin =
Gothic Medium Cond Gre;}{\f140\fswiss\fcharset186\fprq2{\*\panose =
00000000000000000000}Franklin Gothic Medium Cond Bal;}
{\f141\fswiss\fcharset238\fprq2{\*\panose 00000000000000000000}Gill =
Sans Ultra Bold Condensed ;}{\f142\fswiss\fcharset238\fprq2{\*\panose =
00000000000000000000}Tw Cen MT Condensed Extra Bold ;}
{\f143\fdecor\fcharset238\fprq2{\*\panose 00000000000000000000}Onyx =
CE;}{\f144\fdecor\fcharset161\fprq2{\*\panose 00000000000000000000}Onyx =
Greek;}{\f145\fdecor\fcharset162\fprq2{\*\panose =
00000000000000000000}Onyx Tur;}
{\f146\froman\fcharset238\fprq2 Times New Roman =
CE;}{\f147\froman\fcharset204\fprq2 Times New Roman =
Cyr;}{\f149\froman\fcharset161\fprq2 Times New Roman =
Greek;}{\f150\froman\fcharset162\fprq2 Times New Roman Tur;}
{\f151\froman\fcharset186\fprq2 Times New Roman =
Baltic;}{\f152\fswiss\fcharset238\fprq2 Arial =
CE;}{\f153\fswiss\fcharset204\fprq2 Arial =
Cyr;}{\f155\fswiss\fcharset161\fprq2 Arial =
Greek;}{\f156\fswiss\fcharset162\fprq2 Arial Tur;}
{\f157\fswiss\fcharset186\fprq2 Arial =
Baltic;}{\f158\fmodern\fcharset238\fprq1 Courier New =
CE;}{\f159\fmodern\fcharset204\fprq1 Courier New =
Cyr;}{\f161\fmodern\fcharset161\fprq1 Courier New =
Greek;}{\f162\fmodern\fcharset162\fprq1 Courier New Tur;}
{\f163\fmodern\fcharset186\fprq1 Courier New =
Baltic;}{\f236\fswiss\fcharset238\fprq2 Tahoma =
CE;}{\f237\fswiss\fcharset204\fprq2 Tahoma =
Cyr;}{\f239\fswiss\fcharset161\fprq2 Tahoma Greek;}{\f240\fswiss\fcharse=
t162\fprq2 Tahoma Tur;}
{\f241\fswiss\fcharset186\fprq2 Tahoma =
Baltic;}{\f242\fswiss\fcharset238\fprq2 Arial Black =
CE;}{\f243\fswiss\fcharset204\fprq2 Arial Black =
Cyr;}{\f245\fswiss\fcharset161\fprq2 Arial Black =
Greek;}{\f246\fswiss\fcharset162\fprq2 Arial Black Tur;}
{\f247\fswiss\fcharset186\fprq2 Arial Black =
Baltic;}{\f248\fswiss\fcharset238\fprq2 Arial Narrow =
CE;}{\f249\fswiss\fcharset204\fprq2 Arial Narrow =
Cyr;}{\f251\fswiss\fcharset161\fprq2 Arial Narrow =
Greek;}{\f252\fswiss\fcharset162\fprq2 Arial Narrow Tur;}
{\f253\fswiss\fcharset186\fprq2 Arial Narrow =
Baltic;}{\f320\fmodern\fcharset238\fprq1 Lucida Console =
CE;}{\f321\fmodern\fcharset204\fprq1 Lucida Console =
Cyr;}{\f323\fmodern\fcharset161\fprq1 Lucida Console Greek;}
{\f324\fmodern\fcharset162\fprq1 Lucida Console =
Tur;}{\f326\fswiss\fcharset238\fprq2 Lucida Sans Unicode =
CE;}{\f327\fswiss\fcharset204\fprq2 Lucida Sans Unicode =
Cyr;}{\f329\fswiss\fcharset161\fprq2 Lucida Sans Unicode Greek;}
{\f330\fswiss\fcharset162\fprq2 Lucida Sans Unicode =
Tur;}{\f332\froman\fcharset238\fprq2 Book Antiqua =
CE;}{\f333\froman\fcharset204\fprq2 Book Antiqua =
Cyr;}{\f335\froman\fcharset161\fprq2 Book Antiqua Greek;}
{\f336\froman\fcharset162\fprq2 Book Antiqua =
Tur;}{\f337\froman\fcharset186\fprq2 Book Antiqua =
Baltic;}{\f344\froman\fcharset238\fprq2 Bookman Old Style =
CE;}{\f345\froman\fcharset204\fprq2 Bookman Old Style Cyr;}
{\f347\froman\fcharset161\fprq2 Bookman Old Style =
Greek;}{\f348\froman\fcharset162\fprq2 Bookman Old Style =
Tur;}{\f349\froman\fcharset186\fprq2 Bookman Old Style =
Baltic;}{\f362\froman\fcharset238\fprq2 Century Schoolbook CE;}
{\f363\froman\fcharset204\fprq2 Century Schoolbook =
Cyr;}{\f365\froman\fcharset161\fprq2 Century Schoolbook =
Greek;}{\f366\froman\fcharset162\fprq2 Century Schoolbook =
Tur;}{\f367\froman\fcharset186\fprq2 Century Schoolbook Baltic;}
{\f413\fdecor\fcharset161\fprq2 Desdemona =
Greek;}{\f422\fswiss\fcharset238\fprq2 Impact =
CE;}{\f423\fswiss\fcharset204\fprq2 Impact =
Cyr;}{\f425\fswiss\fcharset161\fprq2 Impact =
Greek;}{\f426\fswiss\fcharset162\fprq2 Impact Tur;}
{\f427\fswiss\fcharset186\fprq2 Impact =
Baltic;}{\f458\froman\fcharset238\fprq2 Garamond =
CE;}{\f459\froman\fcharset204\fprq2 Garamond =
Cyr;}{\f461\froman\fcharset161\fprq2 Garamond =
Greek;}{\f462\froman\fcharset162\fprq2 Garamond Tur;}
{\f463\froman\fcharset186\fprq2 Garamond =
Baltic;}{\f464\fscript\fcharset238\fprq2 Comic Sans MS =
CE;}{\f465\fscript\fcharset204\fprq2 Comic Sans MS =
Cyr;}{\f467\fscript\fcharset161\fprq2 Comic Sans MS Greek;}
{\f468\fscript\fcharset162\fprq2 Comic Sans MS =
Tur;}{\f469\fscript\fcharset186\fprq2 Comic Sans MS =
Baltic;}{\f470\fswiss\fcharset238\fprq2 Verdana =
CE;}{\f471\fswiss\fcharset204\fprq2 Verdana =
Cyr;}{\f473\fswiss\fcharset161\fprq2 Verdana Greek;}
{\f474\fswiss\fcharset162\fprq2 Verdana =
Tur;}{\f475\fswiss\fcharset186\fprq2 Verdana =
Baltic;}{\f488\fswiss\fcharset238\fprq2 Trebuchet MS =
CE;}{\f492\fswiss\fcharset162\fprq2 Trebuchet MS =
Tur;}{\f494\fmodern\fcharset238\fprq2 Monotype.com CE;}
{\f495\fmodern\fcharset204\fprq2 Monotype.com =
Cyr;}{\f497\fmodern\fcharset161\fprq2 Monotype.com =
Greek;}{\f498\fmodern\fcharset162\fprq2 Monotype.com =
Tur;}{\f499\fmodern\fcharset186\fprq2 Monotype.com Baltic;}
{\f500\froman\fcharset238\fprq2 Minion Web =
CE;}{\f504\froman\fcharset162\fprq2 Minion Web =
Tur;}{\f505\froman\fcharset186\fprq2 Minion Web =
Baltic;}{\f512\fswiss\fcharset238\fprq2 Albertus Medium =
CE;}{\f516\fswiss\fcharset162\fprq2 Albertus Medium Tur;}
{\f517\fswiss\fcharset186\fprq2 Albertus Medium =
Baltic;}{\f518\fswiss\fcharset238\fprq2 Albertus Extra Bold =
CE;}{\f522\fswiss\fcharset162\fprq2 Albertus Extra Bold =
Tur;}{\f523\fswiss\fcharset186\fprq2 Albertus Extra Bold Baltic;}
{\f524\fswiss\fcharset238\fprq2 Antique Olive =
CE;}{\f528\fswiss\fcharset162\fprq2 Antique Olive =
Tur;}{\f529\fswiss\fcharset186\fprq2 Antique Olive =
Baltic;}{\f530\fswiss\fcharset238\fprq2 CG Omega =
CE;}{\f534\fswiss\fcharset162\fprq2 CG Omega Tur;}
{\f535\fswiss\fcharset186\fprq2 CG Omega =
Baltic;}{\f536\froman\fcharset238\fprq2 CG Times =
CE;}{\f540\froman\fcharset162\fprq2 CG Times =
Tur;}{\f541\froman\fcharset186\fprq2 CG Times =
Baltic;}{\f542\froman\fcharset238\fprq2 Clarendon Condensed CE;}
{\f546\froman\fcharset162\fprq2 Clarendon Condensed =
Tur;}{\f547\froman\fcharset186\fprq2 Clarendon Condensed =
Baltic;}{\f548\fscript\fcharset238\fprq2 Coronet =
CE;}{\f552\fscript\fcharset162\fprq2 Coronet Tur;}
{\f554\fmodern\fcharset238\fprq1 Letter Gothic =
CE;}{\f558\fmodern\fcharset162\fprq1 Letter Gothic =
Tur;}{\f559\fmodern\fcharset186\fprq1 Letter Gothic =
Baltic;}{\f560\fscript\fcharset238\fprq2 Marigold =
CE;}{\f564\fscript\fcharset162\fprq2 Marigold Tur;}
{\f566\fswiss\fcharset238\fprq2 Univers =
CE;}{\f570\fswiss\fcharset162\fprq2 Univers =
Tur;}{\f571\fswiss\fcharset186\fprq2 Univers =
Baltic;}{\f572\fswiss\fcharset238\fprq2 Univers Condensed =
CE;}{\f576\fswiss\fcharset162\fprq2 Univers Condensed Tur;}
{\f577\fswiss\fcharset186\fprq2 Univers Condensed =
Baltic;}{\f578\fswiss\fcharset238\fprq2 Arial MT Black =
CE;}{\f582\fswiss\fcharset162\fprq2 Arial MT Black =
Tur;}{\f584\fscript\fcharset238\fprq2 Benguiat Frisky CE;}
{\f588\fscript\fcharset162\fprq2 Benguiat Frisky =
Tur;}{\f590\fdecor\fcharset238\fprq2 Bertram =
CE;}{\f594\fdecor\fcharset162\fprq2 Bertram =
Tur;}{\f596\fdecor\fcharset238\fprq2 Challenge Extra Bold CE;}
{\f600\fdecor\fcharset162\fprq2 Challenge Extra Bold =
Tur;}{\f602\fswiss\fcharset238\fprq2 Glowworm =
CE;}{\f606\fswiss\fcharset162\fprq2 Glowworm =
Tur;}{\f608\fscript\fcharset238\fprq2 Graphite Light =
CE;}{\f612\fscript\fcharset162\fprq2 Graphite Light Tur;}
{\f614\fscript\fcharset238\fprq2 Lucida Casual =
CE;}{\f618\fscript\fcharset162\fprq2 Lucida Casual =
Tur;}{\f626\fscript\fcharset238\fprq2 Nadianne =
CE;}{\f630\fscript\fcharset162\fprq2 Nadianne =
Tur;}{\f632\fnil\fcharset238\fprq2 Old English CE;}
{\f636\fnil\fcharset162\fprq2 Old English =
Tur;}{\f638\fdecor\fcharset238\fprq2 Party =
CE;}{\f642\fdecor\fcharset162\fprq2 Party =
Tur;}{\f644\froman\fcharset238\fprq2 Poster Bodoni =
CE;}{\f648\froman\fcharset162\fprq2 Poster Bodoni Tur;}
{\f650\froman\fcharset238\fprq2 Pompeii Capitals =
CE;}{\f654\froman\fcharset162\fprq2 Pompeii Capitals =
Tur;}{\f656\fscript\fcharset238\fprq2 Signet Roundhand =
CE;}{\f660\fscript\fcharset162\fprq2 Signet Roundhand Tur;}
{\f662\fswiss\fcharset238\fprq2 Theatre Antoine =
CE;}{\f666\fswiss\fcharset162\fprq2 Theatre Antoine =
Tur;}{\f788\fswiss\fcharset238\fprq2 Franklin Gothic Book =
CE;}{\f789\fswiss\fcharset204\fprq2 Franklin Gothic Book Cyr;}
{\f791\fswiss\fcharset161\fprq2 Franklin Gothic Book =
Greek;}{\f792\fswiss\fcharset162\fprq2 Franklin Gothic Book =
Tur;}{\f793\fswiss\fcharset186\fprq2 Franklin Gothic Book =
Baltic;}{\f794\fswiss\fcharset238\fprq2 Franklin Gothic Demi CE;}
{\f795\fswiss\fcharset204\fprq2 Franklin Gothic Demi =
Cyr;}{\f797\fswiss\fcharset161\fprq2 Franklin Gothic Demi =
Greek;}{\f798\fswiss\fcharset162\fprq2 Franklin Gothic Demi =
Tur;}{\f799\fswiss\fcharset186\fprq2 Franklin Gothic Demi Baltic;}
{\f800\fswiss\fcharset238\fprq2 Franklin Gothic Demi Cond =
CE;}{\f801\fswiss\fcharset204\fprq2 Franklin Gothic Demi Cond =
Cyr;}{\f803\fswiss\fcharset161\fprq2 Franklin Gothic Demi Cond =
Greek;}{\f804\fswiss\fcharset162\fprq2 Franklin Gothic Demi Cond Tur;}
{\f805\fswiss\fcharset186\fprq2 Franklin Gothic Demi Cond =
Baltic;}{\f806\fswiss\fcharset238\fprq2 Franklin Gothic Heavy =
CE;}{\f807\fswiss\fcharset204\fprq2 Franklin Gothic Heavy =
Cyr;}{\f809\fswiss\fcharset161\fprq2 Franklin Gothic Heavy Greek;}
{\f810\fswiss\fcharset162\fprq2 Franklin Gothic Heavy =
Tur;}{\f811\fswiss\fcharset186\fprq2 Franklin Gothic Heavy =
Baltic;}{\f812\fswiss\fcharset238\fprq2 Franklin Gothic Medium =
CE;}{\f813\fswiss\fcharset204\fprq2 Franklin Gothic Medium Cyr;}
{\f815\fswiss\fcharset161\fprq2 Franklin Gothic Medium =
Greek;}{\f816\fswiss\fcharset162\fprq2 Franklin Gothic Medium =
Tur;}{\f817\fswiss\fcharset186\fprq2 Franklin Gothic Medium =
Baltic;}{\f818\fswiss\fcharset238\fprq2 Franklin Gothic Medium Cond =
CE;}
{\f819\fswiss\fcharset204\fprq2 Franklin Gothic Medium Cond =
Cyr;}{\f821\fswiss\fcharset161\fprq2 Franklin Gothic Medium Cond =
Greek;}{\f822\fswiss\fcharset162\fprq2 Franklin Gothic Medium Cond =
Tur;}
{\f823\fswiss\fcharset186\fprq2 Franklin Gothic Medium Cond =
Baltic;}{\f830\fswiss\fcharset238\fprq2 Gill Sans MT =
CE;}{\f836\fswiss\fcharset238\fprq2 Gill Sans MT Condensed =
CE;}{\f842\fswiss\fcharset238\fprq2 Gill Sans Ultra Bold Condensed CE;}
{\f848\fswiss\fcharset238\fprq2 Gill Sans Ultra Bold =
CE;}{\f860\fswiss\fcharset238\fprq2 Gill Sans MT Ext Condensed Bold =
CE;}{\f872\fswiss\fcharset238\fprq2 Haettenschweiler =
CE;}{\f873\fswiss\fcharset204\fprq2 Haettenschweiler Cyr;}
{\f875\fswiss\fcharset161\fprq2 Haettenschweiler =
Greek;}{\f876\fswiss\fcharset162\fprq2 Haettenschweiler =
Tur;}{\f877\fswiss\fcharset186\fprq2 Haettenschweiler =
Baltic;}{\f956\fswiss\fcharset238\fprq2 Tw Cen MT CE;}
{\f962\fswiss\fcharset238\fprq2 Tw Cen MT Condensed =
CE;}{\f968\fswiss\fcharset238\fprq2 Tw Cen MT Condensed Extra Bold =
CE;}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\b=
lue255;\red0\green255\blue0;\red255\green0\blue255;
\red255\green0\blue0;\red255\green255\blue0;\red255\green255\blue255;\re=
d0\green0\blue128;\red0\green128\blue128;\red0\green128\blue0;\red128\gr=
een0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green12=
8\blue128;\red192\green192\blue192;}
{\stylesheet{\qj\sb120\widctlpar\adjustright \fs20\cgrid \snext0 =
Normal;}{\s1\qj\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brd=
rs\brdrw30\brsp20 \jclisttab\tx432\ls50\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid \sbasedon0 \snext2=20
heading =
1;}{\s2\qj\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls50\ilvl1=
\outlinelevel1\adjustright \b\cgrid \sbasedon0 \snext0 heading =
2;}{\s3\qj\fi-720\li720\sb120\keepn\widctlpar
\jclisttab\tx720\jclisttab\tx780\ls50\ilvl2\outlinelevel2\adjustright =
\b\cgrid \sbasedon2 \snext0 heading =
3;}{\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\=
tx864\ls50\ilvl3\outlinelevel3\adjustright \b\cgrid \sbasedon3 \snext0=20
heading =
4;}{\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilv=
l4\outlinelevel4\adjustright \b\fs22\cgrid \sbasedon0 \snext0 heading =
5;}{\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilv=
l5\outlinelevel5\adjustright=20
\i\fs22\cgrid \sbasedon0 \snext0 heading =
6;}{\s7\qj\fi-1296\li1296\sb240\sa60\widctlpar\jclisttab\tx1296\ls50\ilv=
l6\outlinelevel6\adjustright \f1\fs20\cgrid \sbasedon0 \snext0 heading =
7;}{\s8\qj\fi-1440\li1440\sb240\sa60\widctlpar
\jclisttab\tx1440\ls50\ilvl7\outlinelevel7\adjustright \i\f1\fs20\cgrid =
\sbasedon0 \snext0 heading =
8;}{\s9\qj\fi-1584\li1584\sb240\sa60\widctlpar\jclisttab\tx1584\ls50\ilv=
l8\outlinelevel8\adjustright \b\i\f1\fs18\cgrid \sbasedon0 \snext0 =
heading 9;}{\*
\cs10 \additive Default Paragraph =
Font;}{\s15\qj\fi-360\li547\sb120\widctlpar{\*\pn =
\pnlvlblt\ilvl10\ls2047\pnrnot0\pnf8\pnstart1\pnindent360\pnhang{\pntxtb=
?}}\ls2047\ilvl10\adjustright \cgrid \sbasedon0 \snext15 =
Bullet;}{\*\cs16 \additive \sbasedon10=20
page number;}{\s17\sb120\keep\widctlpar\adjustright \fs20\cgrid =
\snext17 CellBody;}{\s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid =
\snext18 =
CellHeading;}{\s19\qj\li1800\sb240\nowidctlpar\tx3600\adjustright =
\b\f4\fs28\cgrid \sbasedon0 \snext19 Date;}{
\s20\qc\sb240\nowidctlpar\adjustright \b\fs20\cgrid \sbasedon0 \snext0 =
Figure;}{\s21\qj\sb240\sl-219\slmult0\nowidctlpar\tx960\tqr\tx9420\tqr\t=
x9840\adjustright \i\f5\fs18\cgrid \sbasedon0 \snext21 =
footer;}{\s22\sb240\sl-280\slmult0\nowidctlpar
\tx960\tqc\tx4339\tqr\tx8479\adjustright \i\f5\cgrid \snext22 =
Footer_Cover;}{\s23\qj\sb120\sl-219\slmult0\nowidctlpar\tqr\tx8611\tqr\t=
x9840\adjustright \i\f5\fs18\cgrid \sbasedon0 \snext23 =
header;}{\s24\sb360\widctlpar\adjustright \b\caps\f1\cgrid=20
\sbasedon1 \snext0 \sautoupd toc =
1;}{\s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
\sbasedon0 \snext25 =
Name;}{\s26\qj\li1685\sb240\nowidctlpar\tx2880\adjustright =
\i\f4\fs36\cgrid \sbasedon0 \snext26 Revision;}{\s27\qc\sl-280\slmult0
\nowidctlpar\adjustright \b\f4\cf16\cgrid \snext27 =
TableTitle;}{\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adju=
stright \fs20\cf1\cgrid \sbasedon0 \snext30 =
Semantics;}{\s29\qj\fi-360\li547\sb120\widctlpar{\*\pn =
\pnlvlblt\ilvl10\ls2047\pnrnot0
\pnf8\pnstart1\pnindent360\pnhang{\pntxtb ?}}\ls2047\ilvl10\adjustright =
\cgrid \sbasedon15 \snext29 =
Dash;}{\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustrigh=
t \fs20\cf1\cgrid \sbasedon28 \snext30 Type;}{
\s31\li288\sb120\sa120\widctlpar\adjustright \b\fs20\cgrid \sbasedon0 =
\snext31 Parameters;}{\s32\qj\li576\sb120\widctlpar\adjustright =
\fs20\cgrid \sbasedon0 \snext32 =
Parameter;}{\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright=20
\fs20\cf1\cgrid \sbasedon30 \snext34 =
Dependencies;}{\s34\qj\li288\sb120\widctlpar\adjustright \fs20\cgrid =
\sbasedon0 \snext31 =
Verification;}{\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\ad=
justright \fs20\cf1\cgrid \sbasedon30 \snext33=20
Applicability;}{\s36\sb240\widctlpar\adjustright \b\fs20\cgrid =
\sbasedon2 \snext0 \sautoupd toc 2;}{\s37\li200\widctlpar\adjustright =
\fs20\cgrid \sbasedon25 \snext0 \sautoupd toc =
3;}{\s38\li400\widctlpar\adjustright \fs20\cgrid=20
\sbasedon28 \snext0 \sautoupd toc 4;}{\s39\li600\widctlpar\adjustright =
\fs20\cgrid \sbasedon0 \snext0 \sautoupd toc =
5;}{\s40\li800\widctlpar\adjustright \fs20\cgrid \sbasedon0 \snext0 =
\sautoupd toc 6;}{\s41\li1000\widctlpar\adjustright \fs20\cgrid=20
\sbasedon0 \snext0 \sautoupd toc 7;}{\s42\li1200\widctlpar\adjustright =
\fs20\cgrid \sbasedon0 \snext0 \sautoupd toc =
8;}{\s43\li1400\widctlpar\adjustright \fs20\cgrid \sbasedon0 \snext0 =
\sautoupd toc 9;}{\s44\qj\fi-360\li360\sb120\widctlpar
\jclisttab\tx360{\*\pn \pnlvlbody\ilvl0\ls42\pnrnot0\pndec =
}\ls42\adjustright \fs20\cgrid \sbasedon0 \snext44 \sautoupd List =
Bullet;}{\s45\qj\sb120\widctlpar\adjustright \fs20\cgrid \sbasedon0 =
\snext45 footnote text;}{\*\cs46 \additive \super \sbasedon10=20
footnote =
reference;}}{\*\listtable{\list\listtemplateid933021884\listsimple{\list=
level\levelnfc23\leveljc0\levelfollow0\levelstartat1\levelspace0\levelin=
dent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 =
\fi-360\li360\jclisttab\tx360 }{\listname=20
;}\listid-119}{\list\listtemplateid-1\listsimple{\listlevel\levelnfc0\le=
veljc0\levelfollow0\levelstartat0\levelspace0\levelindent0{\leveltext\'0=
1*;}{\levelnumbers;}}{\listname =
;}\listid-2}{\list\listtemplateid-1994766790{\listlevel\levelnfc0\levelj=
c0
\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;=
}{\levelnumbers\'01;}\fbias0 \fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers
\'01\'03;}\fbias0 \fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-825\li825\jclisttab\tx825 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext=
\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat2\levelspace0\l=
evelindent0
{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\=
'09;}\fbias0 \fi-825\li825\jclisttab\tx825 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0=
b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid191186669}{\list\listtemplateid-1323032202{\listlevel\levelnfc0=
\leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-645\li645\jclisttab\tx645 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat6\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-645\li645\jclisttab\tx645 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat4\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid318072166}{\list\listtemplateid-546672396{\listlevel\levelnfc0\=
leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\=
'01\'00;}{\levelnumbers\'01;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\'03\'00.=
\'01;}{\levelnumbers\'01\'03;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat4\levelspace0\l=
evelindent0{\leveltext
\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0=20
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'=
03\'05\'07\'09;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0=
b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1
\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'=
06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0 =
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid352266652}{\list\listtemplateid-871755498{\listlevel\levelnfc0\=
leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-495\li495\jclisttab\tx495 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat6\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-495\li495\jclisttab\tx495 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat4\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid413623908}{\list\listtemplateid-452158166{\listlevel\levelnfc0\=
leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\=
'01\'00;}{\levelnumbers\'01;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat4\levelspace0\levelindent0{\leveltext\'03\'00.=
\'01;}{\levelnumbers\'01\'03;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0=20
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'=
03\'05\'07\'09;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0=
b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1
\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'=
06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1800\li1800\jclisttab\tx1800 =
}{\listname =
;}\listid624891100}{\list\listtemplateid-1559598540\listsimple{\listleve=
l\levelnfc23\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\u-39=
13 ?;}{\levelnumbers;}\f3\fbias0 \s44\fi-360\li360\jclisttab\tx360 =
}{\listname =
;}\listid759909709}{\list\listtemplateid867884618\listsimple{\listlevel\=
levelnfc0\leveljc0\levelfollow0
\levelstartat0\levelold\levelspace0\levelindent0{\leveltext\'01\'00;}{\l=
evelnumbers\'01;}}{\listname =
;}\listid1033190212}{\list\listtemplateid1399343956{\listlevel\levelnfc0=
\leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext=

\'01\'00;}{\levelnumbers\'01;}\fbias0 \fi-405\li405\jclisttab\tx405 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\fbias0 =
\fi-405\li405\jclisttab\tx405 }{\listlevel
\levelnfc0\leveljc0\levelfollow0\levelstartat7\levelspace0\levelindent0{=
\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0
{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbi=
as0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers
\'01\'03\'05\'07\'09;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\=
'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080
\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0 =
\fi-1080\li1080\jclisttab\tx1080 }{\listlevel
\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{=
\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'0=
1\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.=
\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\=
'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname ;}\listid1058020587}
{\list\listtemplateid-1\listsimple{\listlevel\levelnfc23\leveljc0\levelf=
ollow0\levelstartat1\levelold\levelspace0\levelindent360{\leveltext\'01\=
u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li360 }{\listname =
;}\listid1059131801}
{\list\listtemplateid-1397715328{\listlevel\levelnfc0\leveljc0\levelfoll=
ow0\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnu=
mbers\'01;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat5\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname =
;}\listid1091587701}{\list\listtemplateid867884618\listsimple{\listlevel=
\levelnfc0\leveljc0
\levelfollow0\levelstartat0\levelold\levelspace0\levelindent0{\leveltext=
\'01\'00;}{\levelnumbers\'01;}}{\listname =
;}\listid1155221946}{\list\listtemplateid-1350535990{\listlevel\levelnfc=
0\leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0
{\leveltext\'01\'00;}{\levelnumbers\'01;}\fbias0 =
\fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\fbias0 =
\fi-780\li780\jclisttab\tx780 }
{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\le=
velindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\fb=
ias0 \fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat2\levelspace0
\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\=
'05\'07;}\fbias0 \fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-780\li780\jclisttab\tx780 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid1365013427}{\list\listtemplateid-421781932\listsimple{\listleve=
l\levelnfc0\leveljc0\levelfollow0\levelstartat0\levelold\levelspace0\lev=
elindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}\f5\fbias0 =
}{\listname ;}\listid1585798300}
{\list\listtemplateid665607334{\listlevel\levelnfc0\leveljc0\levelfollow=
0\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumb=
ers\'01;}\fbias0 \fi-570\li570\jclisttab\tx570 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat7
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\fbias0 \fi-570\li570\jclisttab\tx570 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listname ;}\listid1621764969}{\list\listtemplateid304529758{\listleve=
l\levelnfc0\leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat3\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid1780367330}{\list\listtemplateid867884618\listsimple{\listlevel=
\levelnfc0\leveljc0\levelfollow0\levelstartat0\levelold\levelspace0\leve=
lindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}}{\listname =
;}\listid1833792569}
{\list\listtemplateid237912794{\listlevel\levelnfc0\leveljc0\levelfollow=
0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumb=
ers\'01;}\s1\fi-432\li432\jclisttab\tx432 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\b\i0 \s2\fi-576\li576\jclisttab\tx576 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers
\'01\'03\'05;}\s3\fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\s4\fi-864\li864\jclisttab\tx864 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\s5\fi=
-1008\li1008\jclisttab\tx1008 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\s6\fi-1152\li1152\jclisttab\tx1152 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\s7\fi-1296\li1296\jclisttab\tx1296 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\s8\fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\s9\fi-1584\li1584\jclisttab\tx1584 =
}{\listname =
;}\listid1844272652}{\list\listtemplateid1779308088{\listlevel\levelnfc0=
\leveljc0\levelfollow0
\levelstartat3\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}
\fbias0 \fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\f=
bias0 \fi-870\li870\jclisttab\tx870 }{\listlevel\levelnfc0\leveljc0
\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'07\'00.=
\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\fbias0 =
\fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-870\li870\jclisttab\tx870 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers
\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnum=
bers\'01\'03\'05\'07\'09\'0b\'0d;}\fbias0=20
\fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\lev=
elnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440
\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}=
{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 =
\fi-1440\li1440\jclisttab\tx1440=20
}{\listname =
;}\listid1887254452}{\list\listtemplateid-1\listsimple{\listlevel\leveln=
fc23\leveljc0\levelfollow0\levelstartat1\levelold\levelspace0\levelinden=
t360{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li360 =
}{\listname=20
;}\listid1938361620}{\list\listtemplateid-421781932\listsimple{\listleve=
l\levelnfc0\leveljc0\levelfollow0\levelstartat0\levelold\levelspace0\lev=
elindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}\f5\fbias0 =
}{\listname ;}\listid2008511004}
{\list\listtemplateid26144796{\listlevel\levelnfc0\leveljc0\levelfollow0=
\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbe=
rs\'01;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat4
\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'0=
3;}\fbias0 \fi-660\li660\jclisttab\tx660 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}
\fbias0 \fi-720\li720\jclisttab\tx720 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'0=
5\'07;}\fbias0 \fi-720\li720\jclisttab\tx720 }{\listlevel\levelnfc0
\leveljc0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext=
\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\fbias=
0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0
\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumber=
s\'01\'03\'05\'07\'09\'0b;}\fbias0 \fi-1080\li1080\jclisttab\tx1080 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'=
09\'0b\'0d;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\=
'07\'09\'0b\'0d\'0f;}\fbias0 \fi-1440\li1440\jclisttab\tx1440 =
}{\listlevel\levelnfc0\leveljc0\levelfollow0\levelstartat1\levelspace0\l=
evelindent0{\leveltext
\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03=
\'05\'07\'09\'0b\'0d\'0f\'11;}\fbias0 \fi-1800\li1800\jclisttab\tx1800 =
}{\listname ;}\listid2071222886}}{\*\listoverridetable{\listoverride\lis=
tid-119\listoverridecount0\ls1}
{\listoverride\listid-119\listoverridecount0\ls2}{\listoverride\listid-1=
19\listoverridecount0\ls3}{\listoverride\listid-119\listoverridecount0\l=
s4}{\listoverride\listid-119\listoverridecount0\ls5}{\listoverride\listi=
d-119\listoverridecount0\ls6}
{\listoverride\listid-119\listoverridecount0\ls7}{\listoverride\listid-1=
19\listoverridecount0\ls8}{\listoverride\listid-119\listoverridecount0\l=
s9}{\listoverride\listid-119\listoverridecount0\ls10}{\listoverride\list=
id-119\listoverridecount0\ls11}
{\listoverride\listid-119\listoverridecount0\ls12}{\listoverride\listid-=
119\listoverridecount0\ls13}{\listoverride\listid-119\listoverridecount0=
\ls14}{\listoverride\listid-119\listoverridecount0\ls15}{\listoverride\l=
istid-119\listoverridecount0\ls16}
{\listoverride\listid-119\listoverridecount0\ls17}{\listoverride\listid-=
119\listoverridecount0\ls18}{\listoverride\listid-119\listoverridecount0=
\ls19}{\listoverride\listid-119\listoverridecount0\ls20}{\listoverride\l=
istid-119\listoverridecount0\ls21}
{\listoverride\listid-119\listoverridecount0\ls22}{\listoverride\listid-=
119\listoverridecount0\ls23}{\listoverride\listid-119\listoverridecount0=
\ls24}{\listoverride\listid-119\listoverridecount0\ls25}{\listoverride\l=
istid-119\listoverridecount0\ls26}
{\listoverride\listid-119\listoverridecount0\ls27}{\listoverride\listid-=
119\listoverridecount0\ls28}{\listoverride\listid-119\listoverridecount0=
\ls29}{\listoverride\listid-119\listoverridecount0\ls30}{\listoverride\l=
istid-119\listoverridecount0\ls31}
{\listoverride\listid-119\listoverridecount0\ls32}{\listoverride\listid-=
119\listoverridecount0\ls33}{\listoverride\listid-119\listoverridecount0=
\ls34}{\listoverride\listid-119\listoverridecount0\ls35}{\listoverride\l=
istid-2\listoverridecount1{\lfolevel
\listoverrideformat{\listlevel\levelnfc23\leveljc0\levelfollow0\levelsta=
rtat1\levelold\levelspace0\levelindent360{\leveltext\'01\u-3913 =
?;}{\levelnumbers;}\f3\fbias0 \fi-360\li360 =
}}\ls36}{\listoverride\listid1059131801\listoverridecount0\ls37}
{\listoverride\listid1155221946\listoverridecount0\ls38}{\listoverride\l=
istid1033190212\listoverridecount0\ls39}{\listoverride\listid1938361620\=
listoverridecount0\ls40}{\listoverride\listid1833792569\listoverridecoun=
t0\ls41}{\listoverride\listid759909709
\listoverridecount0\ls42}{\listoverride\listid1091587701\listoverridecou=
nt0\ls43}{\listoverride\listid1887254452\listoverridecount0\ls44}{\listo=
verride\listid1621764969\listoverridecount0\ls45}{\listoverride\listid17=
80367330\listoverridecount0\ls46}
{\listoverride\listid191186669\listoverridecount0\ls47}{\listoverride\li=
stid1058020587\listoverridecount0\ls48}{\listoverride\listid1365013427\l=
istoverridecount0\ls49}{\listoverride\listid1844272652\listoverridecount=
0\ls50}{\listoverride\listid352266652
\listoverridecount0\ls51}{\listoverride\listid318072166\listoverridecoun=
t0\ls52}{\listoverride\listid413623908\listoverridecount0\ls53}{\listove=
rride\listid624891100\listoverridecount0\ls54}{\listoverride\listid20712=
22886\listoverridecount0\ls55}
{\listoverride\listid2008511004\listoverridecount0\ls56}{\listoverride\l=
istid1585798300\listoverridecount0\ls57}}{\*\revtbl =
{Unknown;}}{\info{\title Functional Specification}{\author Current =
User}{\operator Steve Grout}{\creatim\yr1999\mo2\dy5\hr14\min47}
{\revtim\yr1999\mo2\dy16\hr10\min57}{\printim\yr1999\mo2\dy11\hr16\min48=
}{\version62}{\edmins871}{\nofpages25}{\nofwords6451}{\nofchars36774}{\*=
\company Cadence Design Systems =
INC.}{\nofcharsws45161}{\vern113}}\margl2160\margr1440\margt1685\margb16=
13=20
\widowctrl\ftnbj\aenddoc\ftnrestart\lytprtmet\hyphcaps0\viewkind1\viewsc=
ale110\pgbrdrhead\pgbrdrfoot \fet0\sectd =
\psz1\linex0\colsx0\titlepg\sectdefaultcl {\header \pard\plain =
\s23\qj\sb120\sl-219\slmult0\nowidctlpar\tqr\tx8611\tqr\tx9840\adjustrig=
ht=20
\i\f5\fs18\cgrid {\tab Constraint Taxonomy
\par }}{\footer \pard\plain =
\s21\qj\ri360\sb240\sl-219\slmult0\nowidctlpar\tqc\tx4320\tqr\tx8640\adj=
ustright \i\f5\fs18\cgrid {\field{\*\fldinst { DATE }}{\fldrslt =
{\lang1024 02/16/99}}}{\tab Design Constraints Working Group\tab =
}{\field{\*\fldinst {\cs16=20
PAGE }}{\fldrslt {\cs16\lang1024 2}}}{\b\i0\f4=20
\par }}{\footerf \pard\plain =
\s22\sb240\sl-280\slmult0\nowidctlpar\tx960\tqc\tx4339\tqr\tx8479\adjust=
right \i\f5\cgrid {\tab \tab \tab=20
\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang{\pntxta =
.}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang{\pntxta =
.}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang{\pntxta =
.}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang{\pntxta )}}
{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl8
\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta =
)}}\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par=20
\par }\pard \li1685\widctlpar\adjustright {\b Constraint Taxonomy
\par }\pard\plain \s26\ri893\sb240\nowidctlpar\adjustright =
\i\f4\fs36\cgrid {\fs20 Version 042 - with S Grout pass-8
\par }\pard\plain \li1685\widctlpar\adjustright \fs20\cgrid {\b=20
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls42\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls42\adjustright \fs20\cgrid {
Action \endash Telcon with Greg Schulte/Cadence/Ambit on these =
definitions. (done)
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls42\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls42\adjustright {Action \endash=20
complete these Boundary parasitics constraints definitions.
\par }\pard\plain \li1685\widctlpar\adjustright \fs20\cgrid {\b=20
\par=20
\par }\pard\plain \s45\qc\sb120\widctlpar\adjustright \fs20\cgrid =
{Design Constraints Working Group
\par }\pard\plain \qc\sb120\widctlpar\adjustright \fs20\cgrid {
\par Sponsored by
\par Open Verilog International
\par }\pard\plain \s19\qc\sb240\nowidctlpar\tx3600\adjustright =
\b\f4\fs28\cgrid {\fs20 Virtual Socket Interface Alliance
\par }\pard\plain \pagebb\widctlpar\adjustright \fs20\cgrid {\b =
Revision History}{
\par }\pard \sb120\widctlpar\adjustright {
\par }\trowd \trqr\trgaph120 \clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx1182\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15=20
\cltxlrtb \cellx2422\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx5162\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb=20
\cellx8645\pard\plain \s18\nowidctlpar\intbl\adjustright =
\b\f4\fs20\cf1\cgrid {Revision\cell }\pard =
\s18\widctlpar\intbl\adjustright {Date\cell Name\cell Comments\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trqr\trgaph120=20
\clvertalt\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 =
\clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx1182\clvertalt\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 =
\clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx2422\clvertalt
\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 =
\clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx5162\clvertalt\clbrdrt\brdrs\brdrw15 \clbrdrl\brdrs\brdrw15 =
\clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 \cltxlrtb =
\cellx8645\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 7\cell =
1/19/99\cell Steve Grout\cell Continued entering definitions for =
hierarchical boundary parasitics.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 6\cell =
1/5/99\cell Steve Grout\cell Continued entering definitions for =
hierarchical boundary parasitics.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 2\cell =
\cell Steve Grout\cell=20
2d pass list of objects, identify objects with Ambit C/L strawman =
definitions, copied in available Ambit definitions, and adding other =
definitions. Began to define both commands and design objects targeted =
by the commands.\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 1\cell =
\cell Steve Grout\cell First pass of Parasitic Boundary conditions =
\endash=20
discussion of requirements, first list of objects to be defined.\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{0.2\cell 7/6/98\cell Mark Hahn\cell=20
Added a table of contents, clock constraints, and did some =
reformatting\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\trowd \trqr\trgaph120 \clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr
\brdrs\brdrw15 \cltxlrtb \cellx1182\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx2422\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr
\brdrs\brdrw15 \cltxlrtb \cellx5162\clvertalt\clbrdrt\brdrs\brdrw15 =
\clbrdrl\brdrs\brdrw15 \clbrdrb\brdrs\brdrw15 \clbrdrr\brdrs\brdrw15 =
\cltxlrtb \cellx8645\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {0.1\cell =
6/8/98\cell=20
Mark Hahn\cell Initial Creation\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 1\tab}}\pard\plain =
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls50\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20=20
\sect }\sectd \psz1\sbknone\linex0\colsx0\titlepg\sectdefaultcl =
{\header \pard\plain =
\s23\qj\sb120\sl-219\slmult0\nowidctlpar\tqr\tx8611\tqr\tx9840\adjustrig=
ht \i\f5\fs18\cgrid {\tab Constraint Taxonomy
\par }}{\footer \pard\plain =
\s21\qj\ri360\sb240\sl-219\slmult0\nowidctlpar\tqc\tx4320\tqr\tx8640\adj=
ustright \i\f5\fs18\cgrid {\field{\*\fldinst { DATE }}{\fldrslt =
{\lang1024 02/16/99}}}{\tab Design Constraints Working Group\tab =
}{\field{\*\fldinst {\cs16=20
PAGE }}{\fldrslt {\cs16\lang1024 25}}}{\b\i0\f4=20
\par }}{\footerf \pard\plain =
\s22\sb240\sl-280\slmult0\nowidctlpar\tx960\tqc\tx4339\tqr\tx8479\adjust=
right \i\f5\cgrid {\tab \tab \tab=20
\par }}\pard\plain \s24\sb360\widctlpar\adjustright \b\caps\f1\cgrid =
{\b0\ul \page Table Of Contents }{
\par }\pard \s24\sb360\widctlpar\tx400\tqr\tldot\tx8630\adjustright =
{\field\fldedit{\*\fldinst {\caps0 TOC \\o "1-7" }}{\fldrslt =
{\lang1024 1\tab Design Constraints \endash Especially Timing =
Constraints Driving Synthesis\tab }{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385932 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330032000000}}}{\fldrslt {\lang1024 =
5}}}{\lang1024=20
\par }\pard\plain =
\s36\sb240\widctlpar\tx800\tqr\tldot\tx8630\adjustright \b\fs20\cgrid =
{\lang1024 1.1\tab (See ParasaticsDiscussion04sg)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385933 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330033000000}}}{\fldrslt {\lang1024 =
5}}}{\lang1024=20
\par 1.2\tab (See ParasaticsDiscussion04sg)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385934 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330034000000}}}{\fldrslt {
\lang1024 5}}}{\lang1024=20
\par 1.3\tab (See ParasaticsDiscussion04sg)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385935 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330035000000}}}{\fldrslt {
\lang1024 5}}}{\lang1024=20
\par 1.4\tab Hierarchical Parasitic Boundary Conditions\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385936 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330036000000}}
}{\fldrslt {\lang1024 6}}}{\lang1024=20
\par }\pard\plain =
\s37\li200\widctlpar\tx1200\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1\tab Port General Parasitic Boundary Conditions\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385937 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330037000000}}}{\fldrslt {\lang1024 =
6}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.1\tab Port Capacitance - yes\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385938 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330038000000}}}{\fldrslt {\lang1024 =
6}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.1.1.1.1}{\lang1024 \tab }{\lang1024\cgrid0 =
Reference only: set_port_capacitance }{\lang1024 (Ambit)\tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385939 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900330039000000}}}{\fldrslt {\lang1024 =
7}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.1.1.2}{\lang1024 \tab }{\lang1024\cgrid0 Port =
External Capacitance Limit - yes}{\lang1024 \tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385940 \\
h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340030000000}}}{\fldrslt {\lang1024 =
7}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.1.1.2.1}{\lang1024 \tab }{\lang1024\cgrid0 =
Reference only: set_port_capacitance_limit }{\lang1024 (Ambit)\tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385941 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340031000000}}}{\fldrslt {\lang1024 =
8}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.3\tab Port Wire Load Model - yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385942 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340032000000}}}{\fldrslt {\lang1024 =
9}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.3.1\tab Output Port Wire Load (Ambit) \endash =
general\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385943 \\h =
}}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.4\tab Global Capacitance Limit -yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385944 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340034000000}}}{\fldrslt {\lang1024 =
10}}}{\lang1024=20
\par 1.4.1.1.5\tab Input Port Lumped RC Parasitic Model \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385945 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340035000000}}}{\fldrslt {\lang1024 =
11}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.5.1\tab Output Port Internal Lumped RC parasitic =
model \endash general - new\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385946 \\h }}{\fldrslt {
\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.6\tab Output Port Distributed Hierarchical Boundary =
Parasitics (Impedance) \endash general - new\tab }{\field{\*\fldinst =
{\lang1024=20
PAGEREF _Toc443385947 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340037000000}}}{\fldrslt {\lang1024 =
11}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.6.1\tab Unterminated (Open Circuit) Interface Output =
Port Parasitic (impedance) model \endash general -new\tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385948 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340038000000}}}{\fldrslt {\lang1024 =
12}}}{\lang1024=20
\par 1.4.1.1.6.2\tab Terminated (Loaded) Instance (Occurrence) Output =
Port Parasitic (impedance) model - general - new\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385949 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340039000000}}}{\fldrslt {\lang1024 =
12}}}{\lang1024=20
\par 1.4.1.1.6.3\tab Distributed R-C Output Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385950 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350030000000}}}{\fldrslt {\lang1024 =
13}}}{\lang1024=20
\par 1.4.1.1.6.4\tab Distributed R-C-L Output Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385951 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350031000000}}}{\fldrslt {\lang1024 =
13}}}{\lang1024=20
\par 1.4.1.1.6.5\tab Distributed R-C-L-M Output Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385952 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350032000000}}}{\fldrslt {\lang1024 =
14}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.7\tab Input Port Distributed Hierarchical Boundary =
Parasitics (Impedance) \endash general - new\tab }{\field{\*\fldinst =
{\lang1024=20
PAGEREF _Toc443385953 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350033000000}}}{\fldrslt {\lang1024 =
15}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.7.1\tab Unterminated (Open Circuit) Interface Input =
Port Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385954 \\h }{
\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350034000000}}}{\fldrslt {\lang1024 =
15}}}{\lang1024=20
\par 1.4.1.1.7.2\tab Terminated (Loaded) Instance (Occurrence) Input =
Port Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385955 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350035000000}}}{\fldrslt {\lang1024 =
15}}}{\lang1024=20
\par 1.4.1.1.7.3\tab Distributed R-C Input Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385956 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350036000000}}}{\fldrslt {\lang1024 =
16}}}{\lang1024=20
\par 1.4.1.1.7.4\tab Distributed R-C-L Input Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385957 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350037000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par 1.4.1.1.7.5\tab Distributed R-C-L-M Input Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385958 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350038000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par }\pard\plain =
\s37\li200\widctlpar\tx1200\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2\tab Input Port Specific Parasitic Boundary =
Conditions\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385959 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350039000000}}}{\fldrslt {\lang1024 =
18}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.2\tab Input Port External Environment Constraints\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385960 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360030000000}}}{\fldrslt {\lang1024 =
18}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.2.1\tab Number External Sources (Ambit \endash =
num_external_sources) - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385961 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360031000000}}}{\fldrslt {\lang1024 =
18}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.1.2.1.1}{\lang1024 \tab }{\lang1024\cgrid0 =
Reference only \endash set_num_external_sources(Ambit)}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385962 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360032000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.3\tab Input Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385963 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360033000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.3.1\tab Drive Strength : - yes\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385964 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360034000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par }\pard\plain =
\s37\li200\widctlpar\tx1200\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2\tab Output Port Parasitic Boundary Conditions\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385965 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360035000000}}}{\fldrslt {\lang1024 =
20}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1\tab Output port External Environment Constraints\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385966 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360036000000}}}{\fldrslt {\lang1024 =
20}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustrig=
ht \fs20\cgrid {\lang1024 1.4.2.1.1\tab Fanout Load (Ambit) - yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385967 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360037000000}}}{\fldrslt {\lang1024 =
20}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.1.1\tab Fanout \endash same as fanout load\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385968 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360038000000}}}{\fldrslt {\lang1024 =
21}}}{\lang1024=20
\par 1.4.2.1.1.2\tab Fanout Drive \endash same as fanout load\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385969 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360039000000}}}{\fldrslt {\lang1024 =
22}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.2\tab Fanout Load Limit (Ambit) - yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385970 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370030000000}}}{\fldrslt {\lang1024 =
22}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.2.1.2.1}{\lang1024 \tab }{\lang1024\cgrid0 =
Reference - set_fanout_load_limit (Ambit)}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385971 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370031000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.3\tab Number External Sinks - ??? TBD\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385972 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370032000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par 1.4.2.1.4\tab Output Port External Fanout <redundant?>\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385973 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370033000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2\tab Output Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385974 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370034000000}}}{\fldrslt {\lang1024 =
24}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2.1\tab Cell (Block) Drive (Ambit) \endash Drive cell =
-yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385975 \\h =
}{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370035000000}}}{\fldrslt {\lang1024 =
24}}}{\lang1024=20
\par 1.4.2.2.2\tab Effective Drive Internal Capacitance \endash Drive =
Capacitance - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385976 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370036000000}}}{\fldrslt {\lang1024 =
26}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2.2.1\tab Output Port Drive Capability =3D Drive =
Capacitance - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385977 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370037000000}}}{\fldrslt {\lang1024 =
27}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2.3\tab Drive resistance (Ambit) yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385978 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370038000000}}}{\fldrslt {\lang1024 =
27}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.2.2.3.1}{\lang1024 \tab }{\lang1024\cgrid0 =
set_drive_resistance}{\lang1024 \tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385979 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370039000000}}}{\fldrslt {\lang1024 =
28}}}{\lang1024=20
\par 1.4.2.2.3.2\tab Effective Drive Internal Resistance \endash Drive =
Resistance - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385980 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900380030000000}}}{\fldrslt {\lang1024 =
29}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.3\tab Items which are NOT Boundary Parasitics data or =
constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385981 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900380031000000}}}{\fldrslt {\lang1024 =
29}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.3.1\tab Wire Load Model (Ambit) \endash general - =
yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385982 \\h =
}}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.2.3.2\tab Custom Wire Load Mode (Ambit) \endash yes \endash =
not equivalent\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385983 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900380033000000}}}{\fldrslt {\lang1024 =
29}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.3.2.1\tab Output Port Equivalent Custom Wire Load =
\endash general \endash not equivalent\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385984 \\h }{
\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900380034000000}}}{\fldrslt {\lang1024 =
30}}}{\lang1024=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
}}\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\kerning28 =
\sect }\sectd =
\marglsxn1440\margrsxn2160\margtsxn1613\margbsxn1685\psz1\sbkcol\linex0\=
colsx0\titlepg\sectdefaultcl=20
{\*\bkmkstart clock}{\*\bkmkstart parasitics}{\*\bkmkstart =
_Toc443385932}{\*\bkmkstart _Toc422101856}{\*\bkmkend clock}{\*\bkmkend =
parasitics}{\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 1\tab}\pard\plain=20
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls50\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20 Design Constraints \endash Especially =
Timing Constraints Driving Synthesis
{\*\bkmkend _Toc443385932} {\*\bkmkend _Toc422101856}
\par {\*\bkmkstart _Toc443385933}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.1\tab}}\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls50\ilvl1\out=
linelevel1\adjustright \b\cgrid {(See ParasaticsDiscussion04sg)
{\*\bkmkend _Toc443385933}
\par {\*\bkmkstart _Toc443385934}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.2\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc443385934}
\par {\*\bkmkstart _Toc443385935}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.3\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc443385935}
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4\tab}\page {\*\bkmkstart _Toc443385936}Parasitic Boundary =
Conditions{\*\bkmkend _Toc443385936}=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {This =
section defines constraint terms for parasitic boundary conditions and =
may appl. =20
\par Note that, when available and where applicable, the related term =
definition from the Ambit constraint strawman is also included for =
reference.
\par {\*\bkmkstart mark}{\*\bkmkstart _Toc443385937}{\*\bkmkstart =
_Toc432826548}{\*\bkmkstart _Toc434042497}{\*\bkmkstart =
_Toc434061598}{\*\bkmkend mark}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1\tab}}\pard\plain=20
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls54\ilvl2\outlinelevel2\adjustright \b\cgrid {Port General Parasitic =
Boundary Conditions{\*\bkmkend _Toc443385937}
\par }\pard\plain \qj\widctlpar\adjustright \fs20\cgrid {The following =
parasitic constraint definitions apply to both input and output ports =
or port types.}{\cs46\super \chftn {\footnote \pard\plain =
\s45\qj\sb120\widctlpar\adjustright \fs20\cgrid {}}}{
\par {\*\bkmkstart _Toc443385938}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Capacitance
{\*\bkmkend _Toc443385938}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance }{\fs16=20
\par }\pard\plain =
\s28\li288\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the sum of =
the capacitance
at a port of the cell, block or design based on the contribution of =
individual port capacitances from other input and output ports =
connected by nets to a target port.
\par }\pard =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
{\cgrid0 The total capacitance at any port is the sum of the individual =
contributions of external
and internal port capacitances to which the port is connected. A port =
capacitance may be defined within either a design hierarchy or within a =
flattened occurrence design. =20
\par Note that the port capacitance does not include any capacitance =
contribution of the port itself. This capacitance also does not =
include capacitance contribution of the net lying behind the port =
inside the cell.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b DCWG Issue:}{ Discussions with Ambit I believe led =
to the conclusion that this term would necessarily include any possible =
\lquote port self capacitance
\rquote .
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\cgrid0=20
For an input port, the Port Capacitance refers to the individual =
capacitances contributed by all of the other ports that drive to the =
port via a hierarchical net, and the capacitance of the other loads on =
the hierarchical net.=20
\par For out
put ports, the port capacitance refers to the capacitance of all the =
external sinks, and/or external drivers, for the case of a =
multiply-driven net, that are connected to the hierarchical net. This =
capacitance includes capacitance contributions of other i
nput ports of any other external drivers connected to the hierarchical =
net.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b DCWG Issue:}{
The name of this assertion is too generic as the name is appropriate =
for the individual port capacitance contributions that are summed =
within it. It is proposed to be renamed \lquote }{\i total port =
capacitance}{\rquote or \lquote }{\i=20
aggregate port capacitance}{\rquote .
\par }{\b Type}{\tab Parasitic Boundary Condition Assertion
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Ports of a cell definition, cell =
instance, or flattened cell=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Its own capacitance and the =
capacitances of the other ports co
nnected to the same hierarchical net. Also depends on Port Capacitance =
Limit.
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell List of Identifier\cell Only one port on a =
hierarchical net needs to be identified.\cell Identi
fies one or more ports on the target cell or cell instance that will =
have the aggregate capacitance value.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
Target cell or cell instance\cell Identifier\cell Cell must exist in =
the target design hierarchy\cell Name of the cell (if the top cell) or =
cell instance\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\trowd \trgaph108\trleft450\trbrdrt
\brdrs\brdrw30\brdrcf1 \trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10170\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
value\cell Farad Floating value\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.
\par The unit of capacitance will be the same as that used in the =
library or sourcing database.\cell Sum of the individual capacitance =
contributions of the ports of the hierarchical network connected to the =
target port\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row {\*\bkmkstart =
_Toc443385939}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar
\jclisttab\tx1152\ls50\ilvl5\outlinelevel5\adjustright \i\fs22\cgrid =
{\cgrid0 Reference only: set_port_capacitance }{\fs20 =
(Ambit){\*\bkmkend _Toc443385939}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f20\cf1\cgrid0 Command}{\f20\cf1\cgrid0 : }{\f6\fs16\cf1\cgrid0 =
set_port_capacitance
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\b\f1\fs18\cgrid0 :}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance <capacitance> <port_list>
\par }{\b\cgrid0 Description: }{\cgrid0 The }{\f6\fs16\cgrid0 =
set_port_capacitance }{\cgrid0 command specifies the capacitance =
external to the design based on input and output loading from other =
ports and nets connected to the ports of the current module.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0 =
The capacitance at any port is the sum of the external port =
capacitances the port is connected t
o. For an input port the port capacitance refers to the capacitance of =
all the ports of the driver that are connected to the net and the =
capacitance of the other loads on the net. For output ports, the port =
capacitance refers to the capacitance of all the
external sinks, or external drivers, for the case of multiply-driven =
net, that are connected to the net as well as the capacitance of the =
input port of any other external drivers.
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Arguments: =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f21\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par port_list }{\i\f21\cgrid0 \emdash }{\f1\fs18\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
None
\par }{\b\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb240\widctlpar\adjustright {\b\cgrid0 Design Database: =
}{\cgrid0 None
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_current_module, set_port_capacitance_limit
\par }{\b\cgrid0 Examples: }{\cgrid0 This command sets a 3.2 =
capacitance on all output ports of the current module whose names match =
dbus at the start The unit of capacitance will be the same as the unit =
of capacitance used in the library.
\par }\pard \fi720\sb120\widctlpar\adjustright {\f2\cgrid0 =
set_port_capacitance 3.2 [find -port \endash output }{\f2\cf1\cgrid0 =
bus*]
\par {\*\bkmkstart _Toc443385940}{\listtext\pard\plain\s5 \b\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\cgrid0=20
Port Capacitance Limit {\*\bkmkend _Toc443385940}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ }{\cgrid0 Specifies the =
maximum value of the sum of c
apacitance external to the target port based on the sum of all the =
individual capacitance contributions of all input and output ports that =
are hierarchically connected to the target port. This constraint may =
be used to override global port capacitance co
nstraints.
\par This constraint may be specified on a cell interface =
(input}{\f20\cgrid0 or output) port of a design hierarchy, including =
}{\cgrid0 on a port of a top }{\f20\cgrid0=20
level cell. This sets the constraint that the total capacitance (i.e., =
net or wire capacitance and port capacitance) of hierarchical nets =
attached to the ports in the port list do not exceed the specified =
maximum value of capacitance.=20
\par This constraint may be used to override the default capacitance =
limit constraint that may be separately set by the }{\f6\cgrid0 =
Global_Port_Capacitance_Limit constraint}{\f1\cgrid0 .}{\f1\fs18\cgrid0 =

\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard =
\s30\li288\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright {\b =
Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Ports of a cell definition, cell =
instance, or flattened cell occurrence
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for =
capacitance loading of an input or output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
=
=
=
=20
=
=
Target Port name or list\cell List of Identifier\cell=20
The target port(s) must exist within target cell\cell Identifies all =
the ports that are to have the port capacitance limit value\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright=20
\fs20\cgrid {Target cell or cell instance\cell Identifier\cell Cell =
must exist in the target design hierarchy\cell Name of the cell (if the =
top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd=20
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
limit value\cell=20
Farad as Float\cell Zero or greater value in farads. ISO/IEEE postfix =
multiplier may be used, e.g., uF, nF, pF, etc. \cell Maximum value of =
capacitance of the ports and net external to the target ports\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385941}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference only: set_port_capacitance_limit }{(Ambit)}{\cgrid0 =
{\*\bkmkend _Toc443385941}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
{\b\f20\cgrid0 Command:}{\f20\cgrid0 }{\cgrid0 =
set_port_capacitance_limit
\par }{\b\fs18\cgrid0 Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit <capacitance> <port_list>
\par }{\b\fs18\cgrid0 Description:}{\cgrid0 The }{\fs16\cgrid0 =
set_port_capacitance_limit }{\cgrid0 command specifies the limit on the =
}{\fs18\cgrid0 capacitance}{\cgrid0 (maximum value) external to the =
design based on input }{\fs18\cf1\cgrid0=20
and output loading from other ports and nets connected to the ports of =
the current module. }{\cf1\cgrid0 It is used to override design rule =
constraints set by the global attribute
\par }{\b\fs18\cgrid0 set_capacitance_limit:}{\cgrid0 These =
constraints can be specified on top }{\f20\cf1\cgrid0 level input and =
output ports. It sets the constraint that the tot
al capacitances (i.e., wire capacitance and pin capacitance) of nets =
attached to the ports in the port list do not exceed the specified =
capacitance limit. This command overrides the default limit set by the =
}{\f6\fs16\cf1\cgrid0=20
set_global_capacitance_limit }{\f20\cf1\cgrid0 =
command}{\f1\fs18\cf1\cgrid0 .
\par }{\b\fs18\cgrid0 Arguments:}{\cgrid0 =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f21\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f21\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\fs18\cgrid0 =
Options:}{\cgrid0 None
\par }{\b\fs18\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb120\nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_fanout_load_limit, }{\f1\fs18\cf1\cgrid0 =
set_slew_limit, set_port_capacitance, set_num_external_sources, =
set_num_external_sinks, do
_derive_context, do_time_budget, set_global capacitance_limit
\par }{\b\cgrid0 Examples:}{\f1\cgrid0 }{\cgrid0 =
set_port_capacitance_limit 5.0 [find -port dbus*]
\par=20
\par {\*\bkmkstart _Toc443385942}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Wire Load Model
{\*\bkmkend _Toc443385942}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: {\*\bkmkstart save}{\*\bkmkend save} Port Wire =
Load
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ }{\cgrid0 Specifies the wire =
load model for either an input or output po
rt of a hierarchical design, including the top level cell or block. The =
net connected to the port is associated with the specified port wire =
load model and used for wire capacitance and resistance estimation. If =
a net is connected to more than one port wi
t
h a port_wire_load_model assertion, then the worst wire load model is =
computed and used for the net. The library name indicates the location =
of the specified wire load model information. If the library is not =
specified, then the port wire load model infor
mation is used that is defined in the target or default technology.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition, cell =
instance port, or flattened cell occurrence port
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Technology definition of wire load =
model to be associated with a target port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdr=
w10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell \cell Identifies the input port on =
the target cell or cell instance \cell=20
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Cell must exist in the target design =
hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Wire load =
model\cell Identifier\cell \cell=20
Identifies the wire load model information\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb
\brdrs\brdrw10 \cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb=20
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Library\cell Identifier\cell Optional\cell Identifies the =
library that contains the wire load model information.\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\listtext\pard\plain\s6 \i\fs20 \hich\af0\dbch\af0\loch\f0 =
1.4.1.1.3.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\fs20\cgrid0 For Reference =
Only: s
et_port_wire_load (Ambit) \endash =20
\par }\pard\plain =
\s25\qj\fi-720\li720\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: }{\cgrid0 set_port_wire_load}{
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\b =
Semantic definition:}{ }{\cgrid0=20
The set_port_wire_load command specifies the wire load for either an =
input or output top level port of a design. The net connected to the =
port is associated with the specified wire=20
load model, which is used for wire cap and resistance estimation. If a =
net is connected to more than one port with a set_port_wire_load =
assertion, then the worst wire load model is computed and used for the =
net. The library name indicates the location of=20
the specified wire load model. If the library is not specified, then =
the wire load is located from the target technology (the default =
location).
\par }{\b\cgrid0 Syntax:}{\cgrid0 set_port_wire_load ?-library =
<library_name>? <wire_load> <port_list>
\par }{
\par {\*\bkmkstart _Toc443385944}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Global Capacitance Limit{\*\bkmkend _Toc443385944}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Global Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ }{\cgrid0 Specifies the =
default maximum value of aggregate port capacitance defined to exist =
for all or a list of target ports. =20

\par This constraint may be specified on a cell interface port of a =
design hierarchy, includ
ing on a top level port. This defines the constraint of the default =
maximum aggregate port capacitance of hierarchical design network that =
may be associated with a list of target ports. This constraint may be =
overridden for one or more ports by defining a
port capacitance limit constraint.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {DCWG Issue: This constraint may be also overridden by =
defining an aggregate }{\cgrid0 port capacitance assertion for one or =
more target ports.}{
\par }{\cgrid0 DCWG Issue: Global values need to be resolved as part of =
the defaults.}{
\par }{\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for default =
maximum capacitance loading of a port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Default =
External Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Default maximum value of capacitance =
of the ports and net external to the target ports\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\widctlpar\adjustright {
\par \page=20
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.1.1.5\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Non-Lumped Capacitance
Parasitic Boundary Constrants:
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\b DCWG =
Issue:}{ }{The parasitic boundary assertions and constraints defined =
}{in this draft }{
are targeted for use in constraining and/or estimating technologies =
which are amenable to lumped capacitance estimation techniques. It is =
bel
ieved that technologies for smaller feature sizes (e.g., 250nm and =
below) will probably need to be based on use of lumped and/or =
distribution RC, RLC, RLCM, (and possibly AWE-based polynomial) =
approximations for planned and actual nets.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls42\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls42\adjustright \fs20\cgrid {
The following several terms are included in this draft in order to open =
discussions on how to approach constraints and assertions for these =
other net representation models.
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc443385945}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b Lumped RC Port=20
Parasitic Model{\*\bkmkend _Toc443385945}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Lumped RC Parasitic Model
\par }\pard\plain \s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390=
\adjustright \fs20\cf1\cgrid {
Semantic definition: Specifies the distributed parasitic effects of a =
net or netsegment at a given input port as a single lumped-value of =
capacitance and resistance. =20
\par Lumped RC parasitic models for nominal, best-case, and worst-case =
RC parasitic models may be specified from which to calculate =
corresponding nominal, best-case, and/or worst-case net or net-segment =
delay, slew, and other related timing characteristics.

\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The RC parasitic net estimation =
model to be associated with one or more ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
Lumped parasitic R value\cell Float in ohms\cell Equal to or greater =
than zero ohms\cell The R component of the lumped RC representing a =
distributed parasitic model\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd=20
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Lumped =
parasitic C value\cell=20
Float in farads\cell Equal to or greater that zero farads\cell The C =
component of the lumped RC representing a distributed parasitic =
model\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc443385950}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.2\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b=20
Distributed R-C Port Parasitic{\*\bkmkend _Toc443385950} Model
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input port
on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design hierarchy
\cell name of the cell (if the top cell) or cell instance\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {

\par {\*\bkmkstart _Toc443385951}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.3\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b=20
Distributed R-C-L Port Parasitic{\*\bkmkend _Toc443385951} Model
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {
{\*\bkmkstart _Toc443385952}
\par {\listtext\pard\plain\s6 \b\i\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.5.4\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b Distributed R-C-L-M Port =
Parasitics
{\*\bkmkend _Toc443385952}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc443385953}{\*\bkmkstart =
_Toc443385958}{\listtext\pard\plain\s6 \b\i\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.5.5\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright=20
\i\fs22\cgrid {\b Distributed R-C-L-M Port Parasitics{\*\bkmkend =
_Toc443385958} Model
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
{\listtext\pard\plain\s6 \b\i\fs22\cgrid=20
\hich\af0\dbch\af0\loch\f0 1.4.1.1.5.6\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b Port Distributed =
Hierarchical Boundary Parasitics (Impedance)
{\*\bkmkend _Toc443385953}
\par }\pard\plain \widctlpar\adjustright \fs20\cgrid {This section =
defines the distributed R-C, R-L-C, and R-L-C-M parasitic boundary =
conditions for initial estimation of instantiating blocks, cells, and =
macros, and for later backannotated actual parasitics.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {
The approach described in this section currently is being examined for =
applicability to fully accurate hierarchical net timing stored within =
the folded (instance) design hierarchy per the approach published in=20
ISPD98 and other published information that this approach is in used =
within a major EDA supplier.
\par The analysis work and results todate indicates that at least of =
large number of nets may be accurately calculated from the below =
hierarchical two port parasit
ic boundary conditions if the timing is then captured arc-wise in a =
timing view which also have both internal and interface timing arcs. An =
additional instance-port incremental timing offset value is required at =
the \lquote edge\rquote=20
of the block-instance\rquote s interface timing view as part of =
representing the information required for an full instantiation of a =
hierarchical net parasitic model.
\par {\*\bkmkstart _Toc443385954}{\listtext\pard\plain\s7 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.5.6.1\tab}}\pard\plain =
\s7\qj\fi-1296\li1296\sb240\sa60\widctlpar\jclisttab\tx1296\ls50\ilvl6\o=
utlinelevel6\adjustright \f1\fs20\cgrid {\b\f0=20
Unterminated (Open Circuit) Interface Port Parasitic (impedance) =
model{\*\bkmkend _Toc443385954}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Unterminated (Open Circuit) Interface Port =
Parasitic (impedance) Model
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {Semantic =
definition: Specifies an interface input port parasitics model under =
open-circuit conditions. =20
\par This model encapsulates the effects of the loaded and driven =
interface net behind the input port. The open-circuit input port model =
can be used when the cell is instantiated to develop the timing of a =
hierarchical involving the target input port.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Port of a cell definition =
interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The electrical parasitic model of =
net and other connected ports behind the target input port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab Extraction or ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input port on the target cell or cell=20
instance \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target cell \cell Identifier\cell Cell must exist in the =
target design hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Input port =
Parasitic model under external open circuit conditions\cell A group of =
float values representing the unterminated impedance\cell=20
Greater than zero in magnitude\cell Parasitic impedance of the unloaded =
net laying behind the target input port.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385955}
\par {\listtext\pard\plain\s7 \b\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.1.1.5.6.2\tab}}\pard\plain =
\s7\qj\fi-1296\li1296\sb240\sa60\widctlpar\jclisttab\tx1296\ls50\ilvl6\o=
utlinelevel6\adjustright \f1\fs20\cgrid {\b\f0=20
Terminated (Loaded) Instance (Occurrence) Port Parasitic (impedance) =
Model{\*\bkmkend _Toc443385955}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Terminated (Loaded) Instance (Occurrence) Port =
Parasitic (impedance) Model
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies a parasitics model of a =
loaded input port.
\par This input port parasitics model encapsulates the incremental =
effects of an hierarchical net loaded by both the interface loaded net =
and the parasitics of the loaded net at the next level of the design =
hierarchy.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Port of a cell instance =
interface as part of a hierarchical net
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{the contributions of the loaded =
interface net behind the target por
t and the loaded internal net of the next level of the design hierarchy =
when the target cell is instantiated as an occurrence.
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC or extraction
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Input port Parasitic model under external loaded circuit =
conditions\cell=20
A group of float values representing the terminated impedance\cell =
Greater than zero in magnitude\cell Parasitic impedance of the loaded =
net laying behind the target input port.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard=20
\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385959}
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls54\ilvl2\outlinelevel2\adjustright \b\cgrid {Input Port Specific =
Parasitic Boundary Conditions
{\*\bkmkend _Toc443385959}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
following constraint definitions are specific to input ports.
\par {\*\bkmkstart _Toc443385960}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls50\ilvl3\outlinelevel3\adjustright \b\cgrid {
Input Port External Environment Constraints{\*\bkmkend _Toc443385960}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortExternal}{\*\bkmkend InputPortExternal}The =
following are descriptions and constraints foun
d at the input ports of the external implementation or instance of =
block when it is used within a design hierarchy. That is, these =
constraints describe or prescribe those properties of the environment =
surrounding the use of an input port of an instance o
f
a block. These constraints are part of the characteristics of what may =
or should happen at or near the input port of an instance of a block =
when later signals propagate to the input port via the surrounding =
interconnect at the next level of the design hi
erarchy.
\par=20
\par {\*\bkmkstart _Toc443385961}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Number
External Sources (Ambit \endash num_external_sources) - =
yes{\*\bkmkend _Toc443385961}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Number External Sources
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{
Specifies the number of actual external ports that are or may be =
connected to the target port of a cell or cell instance and are driving =
it. }{\cgrid0 This nu
mber is factored into the wire capacitance and wire resistance =
estimation done for the net connected to the target port.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Hierarchical connectivity fan-in
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 \trbrdrb=
\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10147\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number external ports\cell Float\cell \cell Number of =
actual or potential ports external to the target port
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385962}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0 Reference only=20
\endash set_num_external_sources(Ambit){\*\bkmkend _Toc443385962}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f20\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_num_external_sources
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_num_external_sources =
<num_sources> <port_list>
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 Description: =
}{\cf1\cgrid0=20
The set_num_external_sources command can be specified on top level =
input and output ports. This command sets the constraint that the =
number of external sources specified by the command are connected to =
the ports i
n the port list. This number is factored into the wire capacitance and =
wire resistance estimation done for the port nets using the wire load =
models.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f1\fs18\cf1\cgrid0 num_sources \emdash Number of external sources
\par }\pard \sb120\nowidctlpar\adjustright {\f1\fs18\cf1\cgrid0 =
port_list \emdash List of ports
\par }\pard\plain \s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid =
{\f0\cgrid0 Options:
\par Attributes:
\par Design Database:
\par Related Commands:
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\b\cf1\cgrid0 =
Examples:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs18\cf1\cgrid0 =
set_num_external_sinks
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs18\cf1\cgrid0 =
set_port_capacitance
\par do_derive_context
\par do_time_budget}{\f20\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385963}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls50\ilvl3\outlinelevel3\adjustright \b\cgrid {
Input Port Internal Implementation Constraints{\*\bkmkend =
_Toc443385963}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortInternal}{\*\bkmkend InputPortInternal}The =
following are definitions and constraints found at the input ports of =
the internal definit
ion or implementation of a block that will later be reused as a block =
instance in a design hierarchy (and as an occurrence in the unfolded =
design). That is, these definitions and constraints are those =
properties of an input port and possibly its associat
e
d interconnect found within a design definition of a design hierarchy. =
These constraints are part of the characteristics of what may or =
should happen at or near the input port when signals flow in through =
the input port to the rest of the block definiti
on via the associated nearby interconnect.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls42\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls42\adjustright \fs20\cgrid {
None found
\par {\*\bkmkstart _Toc443385965}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls50\ilvl2\outlinelevel2\adjustright \b\cgrid {Output Port Paras
itic Boundary Conditions{\*\bkmkend _Toc443385965}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc443385966}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls50\ilvl3\outlinelevel3\adjustright \b\cgrid {
Output port External Environment Constraints{\*\bkmkend _Toc443385966}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart OutputPortExternal}{\*\bkmkend OutputPortExternal}
The following are descriptions and constraints found at the output =
ports in an external implementation of a cell or block or for an =
instance of a block definition when the block is used
within a design hierarchy. That is, these constraints describe or =
prescribe those properties of the environment surrounding the use of an =
output port of an instance of a block. These constraints are part of =
the characteristics of what may or should hap
pen at or near the output port of an instance of a block when, later, =
signals propagate out through the output port to the interconnect of =
the next higher level part of the design hierarchy.
\par=20
\par {\*\bkmkstart _Toc443385967}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Fanout Load (Ambit) - yes{\*\bkmkend _Toc443385967}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Fanout Load
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {Semantic =
definition:}{\f6\fs16\cgrid0 }{\cgrid0 Specifi
es the expected or budgeted fanout load on the ports of a cell when the =
cell is instantiated. While port capacitance affects timing analysis, =
fanout loads are used during planning the loading of a cell, and later =
to enforce the design rule checks of the=20
application or use a cell.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The number of load or input ports =
that can be connected by a net to an output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell Input or bi-directional port\cell =
Identifies the input port on t
he target cell or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design =
hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Fanout =
value\cell Integer\cell >=3D 0\cell Number of ports that the target =
port may drive\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard=20
\qj\sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s6 \b\i\fs22 \hich\af0\dbch\af0\loch\f0 =
1.4.2.1.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b\cgrid0 For Reference Only =
-}{\f20\cgrid0 }{
\f6\fs16\cgrid0 set_fanout_load (Ambit)
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 set_fanout_load <load> <port_list>
\par }{\b\fs18\cf1\cgrid0 Ambit Description:}{\i\fs18\cgrid0 }{\cgrid0 =
The }{\f6\fs16\cgrid0 set_fanout_load }{\cgrid0=20
command is used to specify the fanout load on the ports of a cell. =
While port capacitance affects timing analysis, fanout loads are used =
to enforce the design rule checks.
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }\pard \fi720\sb120\widctlpar\adjustright {\cgrid0 Ambit =
Arguments:
\par }\pard \fi720\li720\sb120\widctlpar\adjustright {\cgrid0 =
Load;}{\i\f21\cgrid0 }{\f1\fs18\cgrid0 Total fanout load external to =
the cell.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f21\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 List of ports.}{\f1\fs18\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
}{\f6\fs16\cgrid0 None
\par }\pard \widctlpar\adjustright {\b\cgrid0 Attributes:}{\cgrid0 =
fanout_load_limit
\par }{\b\cgrid0 Design Database:}{\cgrid0 =20
\par }\pard \nowidctlpar\adjustright {\b Related =
Commands}{\b\f1\fs18\cf1\cgrid0 :}{\f1\fs18\cf1\cgrid0 =
set_current_module
\par }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385970}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Fanout Load Limit (Ambit) - yes{\*\bkmkend _Toc443385970}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Fanout Load Limit
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid {Semantic =
definition: }{\cf1\cgrid0 Specifies }{\cf1\cgrid0 the fanout load limit =
(maximum value) on }{\cf1\cgrid0 target output }{\cf1\cgrid0 ports =
}{\cf1\cgrid0 for a within a design hierarchy}{
\cf1\cgrid0 . While port capacitance affects timing analysis, fanout =
loads are used to enforce the design rule checks. The design rule =
requirement of a maximum fanout load value is set using the global =
attribute fanout_load_limit. =20
\par }{\f20\cf1\cgrid0 This command overrides the default fanout load =
limit on specific po}{\f20\cf1\cgrid0 rts set by the global attribute, =
global_}{\f6\fs16\cf1\cgrid0 fanout_load_limit}{\f20\cf1\cgrid0 .
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition, cell =
instance, or flattened cell occurrence
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Drive capability of an output port =
of a cell
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Fanout load limit value\cell Integer\cell >=3D 0\cell The =
maximum number of input ports that a cell
output port may drive\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc443385971}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0 Reference - set_fa
nout_load_limit (Ambit){\*\bkmkend _Toc443385971}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\fs18\cf1\cgrid0 Command:}{\f20\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Syntax:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit <load port_list>
\par }\pard \sb120\nowidctlpar\adjustright {\b\cf1\cgrid0 =
Description:}{\cf1\cgrid0 The set_fanout_load_limit command is used to =
specify the fanout load limit (maximum value) on the ports of a cell. =
While port capacitance af
fects timing analysis, fanout loads are used to enforce the design rule =
checks. The design rule requirement of a maximum fanout load value is =
set using the global attribute fanout_load_limit. =20
\par }{\f20\cf1\cgrid0 This command overrides the default fanout load =
limit on specific ports set by the global attribute =
}{\f6\fs16\cf1\cgrid0 fanout_load_limit}{\f20\cf1\cgrid0 .
\par }{\b\fs18\cf1\cgrid0 Arguments:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 load }{\i\f21\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 Fanout load limit on the ports.
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f21\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Options:}{\f1\fs18\cf1\cgrid0 None
\par }{\b\fs18\cf1\cgrid0 Attributes:}{\f1\fs18\cf1\cgrid0 =
fanout_load_limit
\par }{\b\fs18\cf1\cgrid0 Design Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_current_module, =
set_fanout_load
\par }{\b\fs18\cf1\cgrid0 Examples:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_fanout_load_limit 4 [find -port -output =
data*]}{\f20\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Global }{Fanout Load Limit =
(Ambit)
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: }{Global }{Fanout Load Limit
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid {Semantic =
definition: }{\cf1\cgrid0 Specifies }{\cf1\cgrid0 a global =
}{\cf1\cgrid0 fanout load limit (maximum value) }{\cf1\cgrid0 for =
}{\cf1\cgrid0 output ports for a within a design hierarchy
. While port capacitance affects timing analysis, }{\cf1\cgrid0 global =
fanout load limits }{\cf1\cgrid0 are used to }{\cf1\cgrid0 define an =
overall fanout rule}{\cf1\cgrid0 .=20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition, cell =
instance, or flattened cell occurrence
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Overall drive }{capability of =
}{output ports within a design hierarchy and its associated =
technology}{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Global fanout =
}{load limit value\cell Integer\cell >=3D 0\cell The maximum number of =
input ports that a cell
output port may drive\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385972}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Number External Sinks=20
{\*\bkmkend _Toc443385972}(Ambit)
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Number External Sinks=20
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {Semantic =
definition: Specifies }{\cgrid0 that the number }{\cgrid0 of target =
external sink (input or bi-directional) ports }{\cgrid0 are connected =
to the=20
ports in the port list. This number is factored into the wire =
capacitance and the wire resistance estimation done for the port nets =
using the wire load models.}{\cgrid0 The number external sinks =
assertion is specified for }{\cgrid0 top level=20
input and output ports.
\par }{\cgrid0 The number external sinks assertion }{\cgrid0 does not =
add towards the total fanout count for Design Rule Violation(DRV). If =
you do not annotate num}{\cgrid0 ber }{\cgrid0 external}{\cgrid0 =
}{\cgrid0 sinks, then the fanout is }{\cgrid0 set to=20
be a default of }{\cgrid0 1 for the por}{\cgrid0 t (and any other =
internal sink ports }{\cgrid0 of the wire}{\cgrid0 or net within the =
design hierarchy}{\cgrid0 ). }{\cgrid0=20
\par Note that with a n}{\cgrid0 um}{\cgrid0 ber }{\cgrid0 =
external}{\cgrid0 sink assertion}{\cgrid0 , }{\cgrid0 that }{\cgrid0 =
exact number }{\cgrid0 is }{\cgrid0 added to the count of internal =
sinks }{\cgrid0 for the }{\cgrid0 wire}{\cgrid0=20
/net associated with the target port}{\cgrid0 . Therefore, setting =
}{\cgrid0 the assertion, }{\cgrid0 num}{\cgrid0 ber }{\cgrid0 =
external}{\cgrid0 sinks, to 1}{\cgrid0 has no effect.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Technology definition for the =
target output ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\br=
drs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number of external sinks\cell Integer\cell >=3D 0\cell =
Specifies the number of external sink ports to
be associated with a target port for the purpose of later doing net =
timing calculations\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s6 \i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2.1.4.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {For reference only \endash Set =

Num External Sinks (Ambit)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0 =
The set_num_external_sinks command can be specified on top =
level}{\cgrid0 }{\cgrid0 input and output ports. This command =
s}{\cgrid0 ets the constraint that the num}{\cgrid0 ber}{\cgrid0 }
{\cgrid0 of external sinks specified by the command are connected to =
the}{\cgrid0 }{\cgrid0 ports in the port list. This number is factored =
into the wire capacitance}{\cgrid0 }{\cgrid0=20
and the wire resistance estimation done for the port nets using the =
wire}{\cgrid0 }{\cgrid0 load models.
\par It does not add towards the total fan}{\cgrid0 out count for =
Design Rule Viola}{\cgrid0 tion(DRV). If you do not annotate =
set_num_external_sinks, then the}{\cgrid0 }{\cgrid0 fanout is 1 for =
the port (and any other internal sinks of the wire). If you}{
\cgrid0 }{\cgrid0 specify set_num_external_sinks, then you get that =
exact number}{\cgrid0 }{\cgrid0 added to the count of internal sinks =
of the wire. Therefore, setting}{\cgrid0 }{\cgrid0 =
set_num_external_sinks 1 has no effect.
\par For more information on design rule violations, see the =
description for}{\cgrid0 }{\cgrid0 \ldblquote =
set_fanout_load\rdblquote on page 29.
\par Arguments}{\cgrid0 :
\par }{\cgrid0 num_sinks \emdash Number of external sinks
\par port_list \emdash List of ports
\par Options}{\cgrid0 :}{\cgrid0=20
\par Attributes}{\cgrid0 :}{
\par=20
\par {\*\bkmkstart _Toc443385974}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls50\ilvl3\outlinelevel3\adjustright \b\cgrid {
Output Port Internal Implementation Constraints{\*\bkmkend _Toc443385974=
}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart OutputPortInternal}{\*\bkmkend OutputPortInternal}The =
following are definitions and constraints found at the output ports of =
the internal definition or impl
ementation of a block that will later be reused as a block instance in =
a design hierarchy (and as an occurrence in the unfolded design). That =
is, these definitions and constraints are those properties of an output =
port and possibly its associated local i
n
terconnect found within a design definition of a design hierarchy. =
These constraints are part of the characteristics of what may or =
should happen at or near the output port when signals flow to the =
output port via the surrounding interconnect of the int
ernal or local design definition.
\par=20
\par {\*\bkmkstart _Toc443385975}{\listtext\pard\plain\s5 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\fs20=20
Cell (Block) Drive (Ambit) \endash Drive cell{\*\bkmkend =
_Toc443385975}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain \qj\sb120\nowidctlpar\adjustright \fs20\cgrid =
{Semantic definition: }{\cf1\cgrid0 Command set_drive_cell
\par Syntax set_drive_cell ?-early | -late? ?-cell <cell_name>? ?-cell_
\par rise <cell_name>? ?-cell_fall <cell_name> ? ?-library
\par <library_name> ? ?-library_rise <library_name>? ?-library_
\par fall <library_name>? ?-pin <pin_name>? ?-pin_rise
\par <pin_name>? ?-pin_fall <pin_name>? ?-from_pin
\par <from_pin_name> ? ?-from_pin_rise <from_pin_name>? ?-from_
\par pin_fall <from_pin_name> ? ?-source_edge_rise R|F? ?-source_
\par edge_fall R|F? <port_list>
\par Description The set_drive_cell command is used to accurately model =
the drive capability of an external
driver connected to the input port. It is only used for timing =
analysis. It does not affect the electrical properties of the design. =
This means that the capacitance of the output pin of the driving cell =
does not add to the total capacitance of the input=20
port. It computes an offset to the arrival time of an input and also =
changes the slew time used to compute the delay of the cell on the sink =
of the net.
\par The offset to data_arrival_time is computed by taking the total =
delay of the cell for C seen at the inp
ut (not including its own C driver) and sub-tracting the total delay of =
the cell given C load of zero. The total delay means the propagation =
and transition delays, if applicable. The transition delay itself is =
used as the slew value for the delay calculat
ion of the next cell. The library cell that drives the input of the =
design must be identified. The cell can be designated as the driving =
cell for the ports in context by using set_drive_cell command.
\par This command overrides the set_drive_resistance command, per port =
or per net, if it is the last command applied. Also, if set_drive_cell =
is set for a port, set_slew_time is ignored for that port.
\par Arguments port_list }{\i\cf1\cgrid0 \emdash }{\cf1\cgrid0 List of =
ports driven by the driver cell.
\par }{\cgrid0 Command Reference Manual
\par }{\i\cgrid0 Ambit Confidential }{\cgrid0 20 Ambit Design Systems =
Inc.
\par Options -early }{\i\cgrid0 \emdash }{\cgrid0 Specifies that the =
driver provides an early signal, also known as hold.
\par -late }{\i\cgrid0 \emdash }{\cgrid0 Specifies that the driver =
provides a late signal, also known as setup.
\par -cell cell_name }{\i\cgrid0 \emdash }{\cgrid0 Name of the driver =
cell that provides both a rising edge transition driver and a falling =
edge transition driver.
\par -cell_rise <cell_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
cell that provides a rising transition driver.
\par -cell_fall <cell_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
cell that provides a falling transition driver.
\par -library <library_name> }{\i\cgrid0 \emdash }{\cgrid0=20
Name of the library which contains the driving cell. This option is =
used if the same cell provides both the rising and the falling edge =
transitions, or if different cells provide the rising edge and falling =
edge transitions but are in the same library.

\par -library_rise <library_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the library which contains the rising edge transition driver.
\par -library_fall <library_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the library which contains the falling edge transition driver.
\par -pin <pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the output =
port of the driver
cell that drives the signal at the input port of the design. This =
option is required if there are multiple output ports on the driver. If =
there is only one out-put port on the driver cell, use of this option =
is not necessary.
\par -pin_rise <pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
output port of the driver cell which provides the rising edge =
transition drive to the input port of the design.
\par -pin_fall <pin_name>}{\i\cgrid0 \emdash }{\cgrid0 Name of the =
output port of the driver cell which provides the falling edge =
transition drive to the input port of the design.
\par -from_pin <from_pin_name> }{\i\cgrid0 \emdash }{\cgrid0=20
Name of the input port of the driver cell which has an arc to the =
output port of the driver cell which is con-nected to the input port of =
the design. This option is required if there are multiple timing arcs =
in the driv
er cell from its input ports to its output ports. It assumes that the =
same timing arc between the input port and the output port of the =
driver cell is driving both the rising edge transi-tion and the falling =
edge transition on the input port of the design
.
\par -from_pin_rise <from_pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the input port of the driver cell with the controlling timing arc to =
the output port of the driver cell that provides the rising edge =
transition drive to the input port of the design.

\par Command set_drive_cell
\par Command Reference Manual
\par Ambit Design Systems Inc. 21 }{\i\cgrid0 Ambit Confidential
\par }{\cgrid0 -from_pin_fall <from_pin_name> }{\i\cgrid0 \emdash =
}{\cgrid0 Name of the input port of the driver cell with the =
controlling timing arc to the output port of the driver cell that =
provides the falling edge transition dri
ve to the input port of the design.
\par -source_edge_rise R | F }{\i\cgrid0 \emdash }{\cgrid0 Specifies =
whether the rising (R) edge or the falling edge (F) at the =
from_pin_name is controlling the rising edge transition at the input =
port of the design.
\par -source_edge_fall R | F }{\i\cgrid0 \emdash }{\cgrid0 Specifies =
whether the rising edge (R) or the falling edge (F)at the from_pin_name =
is controlling the falling edge transition at the input port of the =
design.=20
\par Attributes
\par Design Database
\par Related Commands set_drive_resistance
\par set_slew_time
\par Examples set_drive_cell -cell IV [ find -input -port * ]
\par set_drive_cell -cell AN3 -from_pin I0 input1
\par Command set_drive_cell
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\f0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh
\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target port name\cell Identifier\cell Input or =
bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc443385976}{\listtext\pard\plain\s5 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\fs20=20
Effective Drive Internal Capacitance \endash Drive Capacitance =
{\*\bkmkend _Toc443385976}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdr=
w30\brdrcf1 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\f0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh
\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target port name\cell Identifier\cell Input or =
bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc443385977}{\listtext\pard\plain\s6 \i\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\fs20=20
Output Port Drive Capability =3D Drive Capacitance{\*\bkmkend =
_Toc443385977}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\f0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh
\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target port name\cell Identifier\cell Input or =
bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc443385978}{\listtext\pard\plain\s5 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls50\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\fs20=20
Drive resistance (Ambit) yes{\*\bkmkend _Toc443385978}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\f0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh
\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target port name\cell Identifier\cell Input or =
bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell=20
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {

\par=20
\par {\*\bkmkstart _Toc443385979}{\listtext\pard\plain\s6 \i\fs20 =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.3.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls50\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\fs20\cgrid0=20
set_drive_resistance{\*\bkmkend _Toc443385979} (Ambit)
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\cf1\cgrid0 Command: }{\cf1\cgrid0 set_drive_resistance
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_drive_resistance ?-rise =
| -fall? ?-early | -late? value
\par port_list
\par }{\b\cf1\cgrid0 Description: }{\cf1\cgrid0=20
The set_drive_resistance command is a simpler version of the =
set_drive_cell command and can be used in many situations where the =
drive resistance can be specified. It is only used for timing analysis. =
It does not affect=20
the electrical properties of the design. It is used to specify the =
drive resistance of a cell. It computes an offset to the arrival time =
of an input and also changes the slew time used to compute the delay of =
the cell on the sink of the net.
\par The arrival ti
me at the input port is modified by adding the RC constant to the =
specified arrival time at the input port. The RC constant is the =
capacitance(C) seen at the input port multiplied by the drive =
resistance (R). The RC value is used as the slew value for the
delay calculation of the next cell. This command overrides the =
set_drive_cell command per port if it is the last command applied. =
Also, if set_drive_resistance is set for a port, set_slew_time is =
ignored for that port.
\par }{\b\cf1\cgrid0 Arguments: }{\cf1\cgrid0 value }{\i\cf1\cgrid0 =
\emdash }{\cf1\cgrid0 Resistance value.
\par port_list }{\i\cf1\cgrid0 \emdash }{\cf1\cgrid0 List of ports for =
which drive resistance is specified.
\par }{\b\cf1\cgrid0 Options: }{\cf1\cgrid0 -rise \emdash Specifies =
that the drive resistance is applicable to only the rising edge =
transition at the input port.
\par -fall \emdash Specifies that the resistance is applicable only to =
the falling edge transition at the input port. If either rise nor fall =
options are specified then the resistance is applied to both =
transitions at the input port.
\par -early \emdash Specifies that the drive resistance should be =
applied to the early arrival time (hold time) for timing analysis.
\par -late \emdash Specifies that the drive resistance should be =
applied to the late arrival time (setup time) for timing analysis.
\par Attributes
\par }{\b\cf1\cgrid0 Design Database: }{\cf1\cgrid0=20
\par }{\b\cf1\cgrid0 Related Commands: }{\cf1\cgrid0 set_drive_cell
\par set_slew_time
\par }{\b\cf1\cgrid0 Examples: }{\cf1\cgrid0 set_drive_resistance=20
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\cf1\cgrid0 [expr 3 * =
[get_cell_drive -cell IV \endash pin A] ] [-input -port * ]
\par }\pard \qj\sb120\widctlpar\adjustright {
\par }{\*\bkmkend _Toc432826548}{\*\bkmkend _Toc434042497}{\*\bkmkend =
_Toc434061598}}

--Boundary_(ID_XjSKs1Lp4MLgH0cHQ2SwYw)--

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