Case sensitivity
----------------
VHDL is normally case insensitive, while Verilog is
normally case sensitive. Escaped names in both languages
are case sensitive.
Escaping
--------
Verilog escaped names start with a backslash and end with a
space. VHDL escaped names start and end with a backslash,
and can include embedded spaces. Some tools allow designers
to omit the escapes, which generally works well as long as
there aren't two distinct objects which have the same name
when escaping is omitted.
Delimiters
----------
VHDL uses () for bus delimiters, while Verilog uses [].
Hierarchy delimiters are usually "/", ".", or "|".
TCL interaction
---------------
By default, when TCL evaluates a string, it will remove
backslashes, treat embedded brackets as a command invocation,
and try to substitute a variable value for any embedded $
characters. This presents problems when TCL strings are
used to represent names of design objects. Some tools
customize the TCL interpreter to treat embedded brackets
as a special case.
Suggestions
-----------
In general, we have to strike a balance between three
conflicting goals:
1. Defining the DCDL name space in a way that matches
particular application programming environments, so
that the object names normally used in a script can be
passed directly as a parameter to a DCDL command.
2. Defining the name space in a way that supports exchanging
DCDL files between multiple applications in a flow.
3. Defining the name space in a way that simplifies
application development.
To address the issues with TCL interpretation, I suggest
we follow two guidelines:
1. DCDL commands or options that always apply to a single
design object should be defined as taking a string
containing that object name. When the object name contains
any characters besides alphanumerics or underscores,
the object name should be strictly quoted using curly
braces. This ensures that when the DCDL command is
interpreted by TCL, the string passed to the application
is exactly the object name. It also facilitates writing
a non-TCL parser for DCDL.
For example, suppose we have a command that specifies the
external driver cell type for a set of input pins, and one
of the options specifies the name of the output port on the
cell which should be used. In the case where the driver cell
type is a RAM, the output port might be DATA_OUT[0].
Then the DCDL command would look like
dcd::driver_cell -cell RAM -output_port {DATA_OUT[0]} ...
and the string DATA_OUT[0] would be passed to the application.
This would be the only legal syntax for a DCDL file used for
interchange purposes, but in the TCL environment it would also
be possible to store the string DATA_OUT[0] in a variable X,
then refer to the variable
set X {DATA_OUT[0]}
dcd::driver_cell -cell RAM -output_port $X ...
2. DCDL commands or options that can apply to more than one
design objects should be defined as taking a list of object
names enclosed in curly braces and separated by white space.
When an object name contains any characters besides alphanumerics
or underscores, the object name should be strictly quoted using
a second level of curly braces.
For example, suppose the driver_cell command was applied to
ports A, B, and \C%2\, where \C%2\ is a VHDL escaped name.
Then the command would look like
dcd::driver_cell -cell RAM -output_port {DATA_OUT[0]} \
{A B {\C%2\}}
and the string passed to the application would be
"A B {\C%2\}". The application would check each entry in
the list to see if it was strictly quoted, and if so, remove
the additional pair of curly braces.
I'm still investigating the issues with the name space
definition. As a suggestion for initial discussion, suppose
we include a name_space command:
dcd::name_space [-verilog | -vhdl | -exchange] \
-hier_delimiter <char>
When -verilog (-vhdl) is specified, all base identifiers are expected
to conform to the Verilog (VHDL) name space, including its definition
of escaping, legal character set, and reserved keywords.
When -exchange is specified, the name space is defined
explicitly in the same way as SDF or GCF. Character by
character escaping is used for any characters besides
alphanumerics and underscore, bus delimiters are
fixed as [] with ranges described as [int:int], and there
are no reserved words.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com