The goal is to pick a subset that is consistent
with existing semantics in various tools, so that
the implementation work for a demo is limited to
a straighforward mapping of the DCDL constraints
into the application's existing constraints (either
internally or through translation by a TCL emulation
layer).
Here's the preliminary definition of the subset that
Greg and I put together and Steve Grout transcribed.
General aspects that are specifically excluded from the
scope of the subset:
- no merging multiple constraints in a min max sesne
- no tags
- no removing constraints
- no partial reset
1. Clock
- waveform definition
- assignment to a pin
- ideal waveforms only
- no external/internal insertion delay
2. Arrival times
- no merging
- ok to reference virtual clocks
3. Required times
- no merging
- ok to reference virtual clocks
- target-based semantics only
4. False paths
- pin, arc, waveform to waveform
- possibly from/to/through pins
5. Multi-cycle paths (MCP)
- pin, arc, waveform to waveform
- possibly from/to/through pins
- potential issue with whether the cycle
adjustments are with respect to the source or
target clock (the Ambit strawman is w.r.t. the source,
clock while most other tools are w.r.t. the target clock)
6. Driver strength
7. External load
8. Wire load model (WLM) selection
- library containing the wire load model
- name of the wire load model
- only one WLM for the whole design (no hierarchical scoping
or enclosed versus top mode)
9. Operating conditions
- unclear whether this should be in terms of a symbolic
name for a combination of P, V, and T values, or in terms
of the P, V, and T values themselves. Not sure which way
OLA does it, which could affect the use of the OLA demo
10. Units
- time, capacitance, resistance, voltage, temperature
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com