Attendees:
  Mark Hahn, Cadence (Chair)
  Bob Dilly, IBM
  Vikas Sharma, IBM
New action items:
      Who         When     What
      ----------  ------   --------
 1.   Bob         4/20     Determine whether an NDA is required for the
                           library data
Open action items:
      Who         When     What
      ----------  ------   --------
 1.   Mark        4/20     Provide a list of BuildGates commands that
                           accept min/max values for best case, worst
                           case operating conditions
 2.   Mark        3/2      Add operating conditions to the taxonomy
                  -> 3/30
                  -> 4/13
                  -> 5/4
 3.   Mark        4/20     Close on DAC demo participation from
                           Synopsys, Synplicity
Closed action items:
      Who         When     What
      ----------  ------   --------
 1.   Jim         1/19     Investigate whether IBM could provide the
                  -> 2/16  Einstimer educational material as a reference
                  -> 3/2
                  -> 3/30
                  -> 4/13
 2.   Mark        3/30     Check on DAC demo participation from
                           Mentor
                  -> 4/6
                  -> 4/13
Next Meeting:
  The next meeting will be a teleconference on 4/20
  from 9-11 am (PDT).
Details:
  1. Review action items
     IBM has concluded that it would be best to contribute through
     direct participation, rather than by providing the Einstimer
     educational material.
     Mark has been in touch with Synplicity, Xilinx, and Altera.
     Synplicity and Altera are fairly interested.  Xilinx declined
     to participate in the demo, although they will watch how the
     standards development goes.
  2. Discuss DAC demo
     We've clarified the origins of the MIPS R4000 design being used
     for testing within IBM; it is definitely public domain, and came
     from http://www.prep.org/.  The web site appears to be dead now.
     PREP acronym stands for Programmable Electronics Performance Corp,
     which was an organization which developed a set of test benches to
     evaluate of synthesis tools (focusing on PLD's).  A comment in the
     Verilog source says "Please feel free to distribute as long as the
     header is attached."
     Cadence has started implementation of the Ambit tcl emulation layer,
     and created a modified version of the test design that uses
     "processor" instead of "R4000", which should avoid any trademark
     infringement issues.
     We talked about whether we might need a specific NDA for the
     demo for the IBM library data.  Bob felt that it probably wasn't
     required, but he planned to check.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com