Re: DC-WG: DCDL DAC demo subset - updated proposal

Mark Hahn (mhahn@cadence.com)
Tue, 20 Apr 1999 10:56:57 -0700

On Apr 20, 7:41am, Vassilios Gerousis wrote:
> Subject: Re: DC-WG: DCDL DAC demo subset - updated proposal
> For the multi-cycle path, you should add conditional statements. Let us take
> an example of an adder with some logic around it. For the add function, one
> clock cycle should be sufficient. For the multiply operation, it may take
> let say three clock cycle. This should be described in the multi-cycle
> constraints.

Vassilios,

This is typically handled by specifying a multi-cycle constraint
with a -through option for the paths through the multiplier.
The DCDL DAC demo subset does include the -through option.

Does this address your concern?

Thanks,
Mark

-- 
Mark Hahn                                          phone: (408) 428-5399
Senior Architect                                   fax:   (408) 428-5959
Cadence Design Systems                             email: mhahn@cadence.com