DC-WG: Update to Vassilios's question

Mark Hahn (mhahn@cadence.com)
Wed, 28 Apr 1999 13:42:38 -0700

On Apr 22, 1:32pm, Vassilios Gerousis wrote:
> On another note (-through for multi-cycle) may not be appropriate (I do not
> know the construct). What I am thing of is the same path but only conditioned
> by boolean operation for different clock cycles. Adders are usually used for
> many other functionality beside add.

I refer to these as case-dependent or mode-dependent constraints.
Other examples include
- constraints on paths associated with RAMs with bidirectional
data input/output pins, where the write enable signal state reflects
the constraint
- constraints applicable during test operation versus normal operation,
particularly if the test clock is muxed with the regular clock

We've talked about these in the past, and I think that the likely
resolution will be to have a -case option on most DCDL commands.
This allows multiple cases to be modeled in a single DCDL file,
which I believe will become important for optimization over the
next couple of years. The problem is that IP blocks will have
lots of modes, each combination of modes for the IP blocks
in the chip (what I call a case) needs to be analyzed, and
optimization needs to satisfy all of the constraints in all
of the cases.

Thanks,
Mark

-- 
Mark Hahn                                          phone: (408) 428-5399
Senior Architect                                   fax:   (408) 428-5959
Cadence Design Systems                             email: mhahn@cadence.com