Attendees:
Mark Hahn, Cadence (Chair)
Bob Dilly, IBM
Vikas Sharma, IBM
Jim Swift, IBM
New action items:
Who When What
---------- ------ --------
1. Bob 5/18 Get authorization to use the IBM logo
2. Mark 5/18 Send Bob the GCF 2.0 spec
Open action items:
Who When What
---------- ------ --------
1. Bob 4/20 Determine whether an NDA is required for the
-> 4/27 library data
-> 5/11
-> 5/18
2. Mark 3/2 Add operating conditions to the taxonomy
-> 3/30
-> 4/13
-> 5/4
-> 5/25
3. Mark 5/4 Work with Jeff and Ed to come up with
-> 5/11 the golden DCDL script for the demo
-> 5/18
Closed action items:
Who When What
---------- ------ --------
1. Vikas 5/11 Send a description of the Einstimer cmds
for operating conditions
2. Mark 5/11 Close on whether it is possible for Cadence
to make their TCL functions available as a
starting point
3. Mark 4/20 Close on DAC demo participation from
-> 5/4 Synplicity, Altera
-> 5/11
Next Meeting:
The next meeting will be a teleconference on 5/11
from 9-11 am (PDT).
Details:
1. Review action items
No progress on closing on the
proceeding with the assumption that no NDA is required.
2. Discuss operating conditions
We talked about issues with selecting the process point for
analysis. Some tools/libraries use a string to identify the
process point, while others use a floating point number. We
need to decide which approach to support (or both), and how
to map between them.
We also discussed identifying multiple operating conditions
up front, then selecting which ones would be used for analysis.
Mark promised to send Bob an early version of the GCF 2.0 draft,
which covers these issues in gory detail.
3. Discuss typical values
We only talked briefly about this, because Mark wasn't able
to send out the proposal far enough in advance of the meeting
for people to review it.
4. Discuss the DAC demo
Synplicity and Actel have decided not to participate in the
demo.
We discussed the flow for the demo. There will be two flows,
one ASIC and one FPGA. The ASIC flow will be based on BuildGates,
Pearl, Einstimer, Silicon Ensemble, and probably Velocity.
The FPGA flow will be based on Leonardo Spectrum, an FPGA
place & route tool (probably Xilinx), and Velocity.
Vikas will send a diagram for the flow IBM envisioned for
Einstimer, and Mark will work on the overall flow diagrams
and message. We tentatively agreed that Einstimer would be
run at the pre-layout analysis stage (immediately prior to
handoff).
Bob pointed out that IBM requires approval for using the IBM
logo; he will follow up on getting the approval.
We talked about the logistics of staging and running the demo.
This is particularly important for the ASIC flow, because tools
from several companies will be involved (for the FPGA flow,
Mentor will be coordinating things). One approach is for
everyone to be familiar with the entire demo, so that we can
alternate presentation times. This requires training and
staging all of the software in advance. Another (less desirable)
approach is to have each company present their portion of the flow.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com