Re: DC-WG: DCDL script for demo

Ed Martinage (ejm@cadence.com)
Tue, 18 May 1999 18:10:01 -0700

Bob,

In the case where the clock frequency of the source clock and that of
the target clock differ, there is a question of which clock the cycle
adjustments are relative to. The Synopsys and GCF semantic is that Hold
offsets (early) are positive additions to the default source clock edges,
and Setup (late) offsets are positive additions to the target clock edges.
>
> By the way, I don't know if I ever asked this, but I'm not exactly
> clear on the intent of ?-target | -source? which is used in
> data_required_time and multi_cycle_path. I looked at the related
> BuildGates commands, but didn't see anything I could relate the
> concept to.

- Ed

-- 
Ed Martinage