Mark
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1 Overview
2 Introduction
2.1 Background
2.2 Purpose
2.4 Overview of DCDL Contents
3 Conventions and Basic Features
3.1 Conventions
3.2 Syntactic description
3.3 Command structure
3.4 Lists as arguments
3.5 Command and Option Name Conventions
3.6 Design Name Spaces
3.7 Design References
3.7.1 Design Object Types
- port, pin, instance, cell, library, etc.
3.7.2 Bit Ranges
3.7.3 Wildcards (?)
3.8 Extension Languages Interactions
3.8.1 Pure DCDL
3.8.2 Embedded DCDL
3.8.3 TCL
3.8.3.1 TCL Name Spaces
3.8.3.2 Embedding DCDL in TCL Scripts
3.9 Persistent Defaults
3.10 Precedence Rules
4 Glossary
5 Header Commands
5.1 DCDL Version
5.2 Name Spaces
5.3 Units
6 Scoping Commands
6.1 Current Module
6.2 Current Instance
7 Multi-Domain Commands
7.1 Operating Conditions
7.2 Modes
7.3 Constant Signals
8 Timing Domain
8.1 Synchronous Theory
8.1.1 Default cycle accounting
8.1.1 Clock domains
8.1.2 Time relative to clock edges
8.1.4 Ideal versus propagated clocks
8.1.5 Clock jitter and other uncertainties
8.2 Clock Commands
8.2.1 Waveforms
8.2.1.1 Ideal waveforms
8.2.1.2 Jitter
8.2.2 Clock domains
8.2.3 Clock roots
8.2.4 Clock arrival times
8.2.5 Clock required times
8.2.6 Derived clocks
8.2.7 Common insertion delay
8.2.8 Clock modes
8.2.8 Clock networks
- Insertion delay, skew, slew, boundaries
8.2.10 Clock uncertainty
8.3 Data Commands
8.3.1 Data arrival times
8.3.2 Data required times
8.3.3 Driving cell type
8.3.4 Drive strength
8.3.5 Slew time
8.3.6 Combination delays
8.3.7 Multi-cycle paths
8.3.8 Disables
8.3.9 False paths
8.3.10 Borrow limits (level-sensitive latches)
8.3.11 Slew limits
9 Parasitics Domain
9.1 Port capacitances
9.3 Port external sources
9.4 Port external sinks
9.5 Wire load models
9.6 Load limits
9.7 Fanout limits
10 Compliance
10.1 Errors and warnings
Appendixes
I. Complete syntax (BNF)
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com