Included below is information on what Einstimer terms as phase/clock renames and
adjust signals. These capabilities are extensively used within our timing
methodology.
Though numerous design scenarios require such constraints I am using a clock
splitter
as a example. Could we put this on the agenda for discussion next week.
Thanks
-Vikas
Timing Clock Splitters
===================================================================================
This describes how the phase renames and adjust signal descriptions are created
for clock splitter designs.
A clock splitter is typically used to convert a single oscillator clock input
into multiple clocks.
Consider the case where an OSC clock is input to the clock splitter cell shown
below.
Assume, from the delay rule, that the behavior of the block includes an
inverting segment between pins A1 and O2 and
a non-inverting segment between pins A1 and 01.
The phase file must define the OSC clock. For example:
OSC 0.0 5.0 10.0
The primary input file will describe the arrival time, slews and polarity for
the input pin A1. For example:
A1 +OSC 0.0 5.0 1.0 1.0
Assume the primary input assertion is the +OSC assertion described above.
Let's suppose the delays are such that the AT (Arrival Time) rising at O1 = 0.1
and AT falling at O1 = 5.1 and, similarly, the AT
rising at O2 = 5.1 and AT falling at O2 = 0.1.
and O2 respectively.
---- O1 (OSC+)
| |---
A1----| | O2 (OSC-)
+OSC | |---
|____|
While not required, if you want to change the outputs to contain phases for
different clocks, you may have to make
adjusts to the arrival times at the outputs to match the new phase descriptions.
Let us assume that you would like phases based on L1 and L2 clocks at pins O1
and O2 respectively.
In this case, clocks OSC and the target clocks L1 and L2 must be defined. Assume
the following clock
descriptions:
OSC 0.0 5.0 10.0
L1 0.0 5.0 10.0
L2 5.0 10.0 10.0
Assume the primary input file describes the OSC clock input to the chip as
below:
+OSC 0.0 5.0 r-slew f-slew
The default behavior of the timer would be to create OSC+ and OSC- phases for
pins O1 and O2 respectively.
---- O1 (L1)
| |---
A1----| | O2 (L2)
+OSC | |---
|____|
However, assume we want the phases renamed to +L1 and +L2 respectively. So, we
add the following entries
rename_phase -pins "box/O1" -phase * -new_phase "L1+" -early -late
rename_phase -pins "box/O1" -phase * -new_phase "L2+" -early -late
This results in the following times at the outputs of the clock splitter.
AT at O1 = phase(L1+) ( AT-r = 0.1 AT-f = 5.1 )
AT at O2 = phase(L2+) ( AT-r = 5.1, AT-f = 0.1 )
Note:
The arrival times for phase L2+ do not match the phase description.
Specifically, we want to look at the waveform
as ( AT-r = 5.1, AT.f = 0.1 + 10.0 = 10.1 ). This is just a periodic
shift, which is to be explicitly instructed to the
timing system.
The adjust signal command adjusts the arrival time at the O2 pin,
adjust_signal -pins "box/O2" -phase L2+ -time 10 -fall
The resulting outputs are:
AT at O1 = phase(L1+) ( AT-r = 0.1 AT-f = 5.1 )
AT at O2 = phase(L2+) ( AT-r = 5.1, AT-f = 10.1 )
The rename_clock command renames and adjusts the waveform of a clock at a
particular point.
Syntax
rename_clock
-ports {"port1" "port2" ...}
-nets {""net1" "net2"...}
-pins {pin1 pin2 ...};
-clock "clock_name"
-new_clock "new_clock_name"
-inverted
-rise_adj #.#
-fall_adj #.#;
The rename_phase command allows you to change the phases of the arrival times
propagating through the pins.
Syntax
rename_phase
-ports {"port1" "port2", ...}
-nets {""net1" "net2",...}
-pins {pin1 pin2 ...};
-phase "current_phase_name"
-new_phase "new__phase_name"
-early | -late;
The adjust_signal command adjusts the arrival and required times flowing through
particular points in the circuit by a
specified time amount.
Syntax
adjust_signal
-ports {"port1" "port2" ...}
-nets {""net1" "net2"...}
-pins {pin1 pin2 ...};
-clock "clock_name"
-inverted
-clock_phase
-rise | -fall;
-time "value"