After looking into DCDL waveform /derived waveform, clock/derived clock
semantics, here's
my two cents..........
Einstimer command explanation ---->
Einstimer command ; adjust_and_rename
et::adjust_and_rename
{ -phase string }
{ -time double }
{ -new_phase string }
{ -ports list of strings + -nets list of strings + -pins list of
strings + -cell_type string}
optional flags,
[ -rise + -fall ]
[ -early + -late ]
The adjust and rename command in Einstimer adjusts the arrival times
flowing through particular points in the circuit by a specified delta
(-time flag)
and performs rename too. The new phase defined has its waveform properties
previously defined. Fanout downstream logic from asserted design instance
has its arrival time adjusted by user specified delta. While phase
adjustments for any
setup / hold test downstream uses the new phase propeties. Einstimer adds
to the exisitng arrival time at that port or pin, the user specified delta
adjust.
DCDL capabilties
1. Since there is no phase concept (data/clock), any conversion from clock
to data
and vice versa is precluded while moving design data between Einstimer and
DCDL
2. The clock command could possibly be used to change clock phase (eg:
clk_b to clk_a)
at a given design instance ( pin or port). Given that waveforms clk_b and
clk_a are defined,
the clock command can be used to associate the waveform at the required
design instance.
But this does not allow a user specified "time" adjust to be made to the
signal.
3. Alternatively derived_waveform could be used to rename clock at a pin
or port in association with
derived clock. The phase option to the derived waveform can be used with
a value of 1. This would
create an identical waveform as the exisiting one. Again the issue of
being able to assert a signal
adjust is not addressed.
Comments/questions are welcome.
-Thanks
Vikas