Subject: DC-WG: Some issues for next meeting
From: Paul-Cesar Bonnel (pcbonnel@cadence.com)
Date: Mon Aug 14 2000 - 16:24:34 PDT
Hello everyone,
Here are some commands to be discussed on Tuesday meeting.
TOPICS
- data_arrival_time
- data_required_time
- departure_time
- external_delay
- first issue: -source/-target in data_arrival_time and
data_required_time:
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This option is neither in GCF nor in synopsys command. (but partially in
BG's set_external_delay).
I have a simple figure to explain the goal of that option in the
document source_target.pdf
The value given in the constraint can be related to the cycle of the
launching edge (-source) or to the cycle of the capturing edge
(-target).
On the example, we can specify:
data_arrival_time -waveform PH1 -source -ports {IN} 15
or
data_arrival_time -waveform PH2 -target -ports {IN} -3 (three before
clock edge at 18).
If no keyword is specified, -source is implied for data_arrival_time and
-target is implied for data_required_time. (note that BG's
data_required_time is actually -source semantics).
- second issue
--------------
The second issue concerns combinational delay with these commands.
Here are five cases. The corresponding figures are in
combinational_delay.pdf.
1- Tools are consistent in modeling for arrival and required times
referenced to clock edge and relating those constraints to clock edges
at internal registers.
2- Tools are also consistent in modeling for conditional delays outside
a module and relating those delays to combinational logic inside the
module.
3- Tools are also consistent in modeling for arrival times and required
times referenced to clock edges and relating those constraints to
combinational logic inside the module.
4- The semantics for relating external combinational delays to clock
edges at internal registers is troublesome. Some tools make up a virtual
clock based on the least common multiple of the clock edges inside the
module related to the port, but the edges used are fairly arbitrary.
5- What to do with a mixture?
Thanks
-Paul
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