(GCF 
  
  (HEADER 

    (VERSION "1.1")
    (DESIGN "fake design")
    (DATE "Thu Sep  4 13:54:29 1997")
    (PROGRAM "gcfwtest" "1.0" "Cadence Design Systems, Inc.")
    (DELIMITERS "/()")
    (TIME_SCALE 1.0E-09)
    (CAP_SCALE 1.0E-12)
    (LENGTH_SCALE 1.0E-06)
    (AREA_SCALE 1.0E-12)
    (POWER_SCALE 1.0E-03)
    
    (EXTENSION "gcftest" 
      HeaderInfoExtension
    )
  
  ) // HEADER
  
  (GLOBALS 
    
    (GLOBALS_SUBSET ENVIRONMENT 
      ("PROCESS_LABEL": PROCESS 0.80 1.20)
      (VOLTAGE 3.10 3.50)
      (TEMPERATURE -20.00 40.00)
      (OPERATING_CONDITIONS "bccom" 0.80 3.50 -20.00)
      (VOLTAGE_THRESHOLD 20.00 80.00)
      
      (EXTENSION "gcftest" 
        EnvGlobalsExtension
      )
      
      (EXTENSION "CTLF_FILES" 
        (
          lib.ctlf
          ram1.ctlf
          ram2.ctlf
        )
      )
    
    ) // GLOBALS_SUBSET ENVIRONMENT
    
    (GLOBALS_SUBSET TIMING 
      
      ("CLK1_LABEL": WAVEFORM "CLK1_WAVEFORM" 10.00 
        (posedge 0.00 0.10)
        (negedge 5.00)
      )
      
      ("CLK2_LABEL": WAVEFORM "CLK2_WAVEFORM" 20.00 
        (posedge 0.00 0.10)
        (negedge 10.00)
      )
      
      (LEVEL 1 
        
        ("DCLK1": DERIVED_WAVEFORM "DERIVED_CLK1_WAVEFORM" "CLK1_WAVEFORM" 
          (PHASE_SHIFT 5.00)
        )
        
        ("DCLK2": DERIVED_WAVEFORM "DERIVED_CLK2_WAVEFORM" "CLK2_WAVEFORM" 
          (PHASE_SHIFT 10.00)
          (SKEW_ADJUSTMENT 
            (posedge 0.00 0.10)
            (negedge 0.20)
          )
        )
        
        ("DCLK3": DERIVED_WAVEFORM "DERIVED_CLK3_WAVEFORM" "CLK3_WAVEFORM" 
          (PERIOD_MULTIPLIER 5)
        )
        
        ("DCLK4": DERIVED_WAVEFORM "DERIVED_CLK4_WAVEFORM" "CLK4_WAVEFORM" 
          (PHASE_SHIFT 20.00)
        )
        
        ("DCLK5": DERIVED_WAVEFORM "DERIVED_CLK5_WAVEFORM" "CLK5_WAVEFORM" 
          (PHASE_SHIFT 25.00)
          (SKEW_ADJUSTMENT 
            (posedge 0.00 0.10)
            (negedge 0.20)
          )
        )
        
        (CLOCK_GROUP "clock_group_1"
          "CLK2_WAVEFORM"
          "CLK3_WAVEFORM"
        )
        
        (CLOCK_GROUP "clock_group_2"
          "CLK4_WAVEFORM"
          "CLK5_WAVEFORM"
        )
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        TimingGlobalsExtension
      )
    
    ) // GLOBALS_SUBSET TIMING
    
    (EXTENSION "gcftest" 
      GlobalsSubsetExtension
    )
  
  ) // GLOBALS
  
  (CELL () 
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 5.31
            in(1) 
          )
          
          (BORROW_LIMIT 3.62
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 9.48 9.65
          in(1) 
        )
        
        (EXTERNAL_LOAD 7.02 7.25
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 4.95 5.07
            in(1) 
          )
          
          (EXTERNAL_FANOUT 0.84 1.23
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 2.77 3.14
          in(1) 
        )
        
        (INTERNAL_LOAD 9.83 10.37
          in(2) 
        )
        
        (LOAD 7.66 8.30
          in(1) 
        )
        
        (LOAD 7.67 8.45
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 8.23 8.38
            in(1) 
          )
          
          (INTERNAL_FANOUT 6.25 6.57
            in(2) 
          )
          
          (FANOUT 3.47 4.39
            in(1) 
          )
          
          (FANOUT 5.20 5.60
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 6.07 6.85
        in(1) 
      )
      
      (AVG_NET_POWER 9.32 10.19
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL (CELLTYPE "mylib" "cella")
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 9.34
            in(1) 
          )
          
          (BORROW_LIMIT 8.17
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 3.89 4.25
          in(1) 
        )
        
        (EXTERNAL_LOAD 2.00 2.83
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 4.16 4.62
            in(1) 
          )
          
          (EXTERNAL_FANOUT 9.79 9.92
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 2.13 3.08
          in(1) 
        )
        
        (INTERNAL_LOAD 7.37 7.78
          in(2) 
        )
        
        (LOAD 7.80 8.56
          in(1) 
        )
        
        (LOAD 9.57 9.60
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 3.19 3.94
            in(1) 
          )
          
          (INTERNAL_FANOUT 2.43 3.02
            in(2) 
          )
          
          (FANOUT 0.43 1.39
            in(1) 
          )
          
          (FANOUT 3.19 3.25
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 4.42 5.33
        in(1) 
      )
      
      (AVG_NET_POWER 5.72 5.84
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL (CELLTYPE "mylib" "cellb"
    "view1"
    "view2")
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 5.95
            in(1) 
          )
          
          (BORROW_LIMIT 5.20
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 4.77 5.18
          in(1) 
        )
        
        (EXTERNAL_LOAD 8.73 9.16
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 3.58 3.96
            in(1) 
          )
          
          (EXTERNAL_FANOUT 0.43 0.59
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 5.22 5.92
          in(1) 
        )
        
        (INTERNAL_LOAD 0.97 1.37
          in(2) 
        )
        
        (LOAD 7.73 7.98
          in(1) 
        )
        
        (LOAD 3.43 3.66
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 2.98 3.28
            in(1) 
          )
          
          (INTERNAL_FANOUT 8.87 8.91
            in(2) 
          )
          
          (FANOUT 6.51 6.91
            in(1) 
          )
          
          (FANOUT 6.76 7.50
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 9.38 9.61
        in(1) 
      )
      
      (AVG_NET_POWER 8.38 9.35
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL single_instance 
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 8.22
            in(1) 
          )
          
          (BORROW_LIMIT 7.55
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 1.59 1.87
          in(1) 
        )
        
        (EXTERNAL_LOAD 1.35 2.22
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 7.50 7.71
            in(1) 
          )
          
          (EXTERNAL_FANOUT 1.40 1.69
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 8.03 8.25
          in(1) 
        )
        
        (INTERNAL_LOAD 5.63 6.35
          in(2) 
        )
        
        (LOAD 1.98 2.97
          in(1) 
        )
        
        (LOAD 2.50 2.93
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 7.55 8.41
            in(1) 
          )
          
          (INTERNAL_FANOUT 8.95 9.93
            in(2) 
          )
          
          (FANOUT 3.95 4.39
            in(1) 
          )
          
          (FANOUT 1.27 1.73
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 2.38 3.36
        in(1) 
      )
      
      (AVG_NET_POWER 6.53 7.13
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL 
    ( 
      instance1 
      instance2 
    )
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 2.87
            in(1) 
          )
          
          (BORROW_LIMIT 7.98
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 4.76 4.92
          in(1) 
        )
        
        (EXTERNAL_LOAD 2.46 3.40
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 6.14 7.13
            in(1) 
          )
          
          (EXTERNAL_FANOUT 4.77 5.57
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 7.44 7.82
          in(1) 
        )
        
        (INTERNAL_LOAD 4.80 5.33
          in(2) 
        )
        
        (LOAD 0.98 1.58
          in(1) 
        )
        
        (LOAD 3.47 3.62
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 7.80 8.51
            in(1) 
          )
          
          (INTERNAL_FANOUT 4.46 5.17
            in(2) 
          )
          
          (FANOUT 0.95 1.92
            in(1) 
          )
          
          (FANOUT 5.51 6.25
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 5.79 6.43
        in(1) 
      )
      
      (AVG_NET_POWER 7.82 8.00
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL arrayed_instance(0) 
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 3.30
            in(1) 
          )
          
          (BORROW_LIMIT 7.13
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 5.65 6.07
          in(1) 
        )
        
        (EXTERNAL_LOAD 3.07 3.51
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 5.66 6.14
            in(1) 
          )
          
          (EXTERNAL_FANOUT 6.07 6.48
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 1.30 1.56
          in(1) 
        )
        
        (INTERNAL_LOAD 0.36 1.33
          in(2) 
        )
        
        (LOAD 1.15 1.52
          in(1) 
        )
        
        (LOAD 6.47 6.82
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 5.53 5.89
            in(1) 
          )
          
          (INTERNAL_FANOUT 5.65 6.13
            in(2) 
          )
          
          (FANOUT 1.64 2.25
            in(1) 
          )
          
          (FANOUT 1.72 2.28
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 2.92 3.79
        in(1) 
      )
      
      (AVG_NET_POWER 8.35 9.20
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL parent_instance/escaped_arrayed_instance\\\(0\\\:1\\\)(0:16) 
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 9.55
            in(1) 
          )
          
          (BORROW_LIMIT 5.57
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 6.55 7.24
          in(1) 
        )
        
        (EXTERNAL_LOAD 2.64 2.75
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 8.15 8.34
            in(1) 
          )
          
          (EXTERNAL_FANOUT 4.23 4.58
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 8.39 8.53
          in(1) 
        )
        
        (INTERNAL_LOAD 2.63 2.80
          in(2) 
        )
        
        (LOAD 4.80 5.18
          in(1) 
        )
        
        (LOAD 5.05 5.55
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 3.52 4.04
            in(1) 
          )
          
          (INTERNAL_FANOUT 1.21 1.73
            in(2) 
          )
          
          (FANOUT 6.07 6.80
            in(1) 
          )
          
          (FANOUT 5.57 5.91
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 8.02 8.61
        in(1) 
      )
      
      (AVG_NET_POWER 2.67 3.34
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (CELL hier1\\\[0\\\]/hier2(*)/hier3\\\(0\\\:15\\\)\\\/hier4_with\\\.dot\\\/hier5_with\\\/slash/leaf(0:15) 
    
    (EXTENSION "gcftest" 
      CellBodyExtension
    )
    
    (SUBSET TIMING 
      
      (ENVIRONMENT 
        
        (CLOCK "CLK1_WAVEFORM"
          clock_input_pin_2 
          clock_input_pin_3 
        )
        
        (CLOCK "CLK2_WAVEFORM"
          clock_input_pin_4 
          clock_input_pin_5 
        )
        
        (ARRIVAL (posedge "CLK1_WAVEFORM") 0.12 10.12 1.12 12.12
          in_a(0:31) 
          in_b\[0\] 
        )
        
        (ARRIVAL (negedge "CLK2_WAVEFORM") 
          (negedge 5.00)
          in_c(0) 
          in_d(1) 
        )
        
        ("ARRIVAL_3": ARRIVAL (negedge "CLK3_WAVEFORM") 
          (posedge 10.00 15.00)
          in_c 
        )
        
        (DEPARTURE (posedge "CLK1_WAVEFORM") 20.00 19.00 -15.50 -17.00 
          a_long_name/b/c/data_out(0:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 20.00 20.00 -15.00 -15.00 
          a/b/data_out(15:31) 
        )
        
        (DEPARTURE (negedge "CLK2_WAVEFORM") 
          (negedge 18.00 18.00)
          data_out 
        )
        
        (EXTERNAL_DELAY 
          (negedge 5.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
        )
        
        (EXTERNAL_DELAY 1.00 2.00 3.00 4.00 
          (TO
            "a/b/c/reg_z(0)/D"
            "out(0)"
          )
        )
        
        (EXTERNAL_DELAY 
          (posedge 5.00 6.00) 
          (FROM
            "a/b/c/reg_c(0)/Q"
            "in(0)"
          )
          (FROM
            "a/b/c/reg_d(1)/Q"
          )
        )
        
        (INPUT_SLEW 2.10 3.00 1.80 1.90
          in(0) 
        )
        
        (INPUT_SLEW 4.20 6.00 3.60 3.80
          in(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cella") )
          in(0) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellb") IN1 OUT )
          (
            (PARALLEL_DRIVERS 2)
          )
          in_a(1) 
          in_b(1) 
        )
        
        (DRIVER_CELL 
          ( (CELLTYPE "mylib" "cellc") OUT )
          (
            posedge 
            
            (INPUT_SLEW 2.10 3.00 1.80 1.90
              IN1 
            )
            
            (INPUT_SLEW 1.00
              IN2 
            )
          )
          in_c(2) 
          in_d(2) 
        )
        
        (DRIVER_STRENGTH 3.20 4.10
          in(0) 
        )
        
        (DRIVER_STRENGTH 6.40 8.20
          in(1) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_SLEW 2.10 3.00 1.80 1.90
            dff/d(0) 
          )
          
          (INTERNAL_SLEW 4.20 6.00 3.60 3.80
            dff/d(1) 
          )
          
          (CONSTANT 1 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
          
          (CONSTANT 0 
            a_long_name/b/c/data_in(0) 
            a/b/c/data_in(1) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (EXCEPTIONS 
        
        (DISABLE 
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          setup posedge 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
        )
        
        ("DISABLE_LABEL": DISABLE 
          a/b/c/in1 
        )
        
        (DISABLE 
          a/b/c 
        )
        
        (DISABLE 
          (ARC 
            a/b/c/in1  
            a/b/c/out 
          )
          a/b/d/in1 
          a/b/e 
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
        )
        
        (MULTI_CYCLE 
          (SETUP 3)
          (HOLD 1)
          (
            (FROM
              "a/b/c/reg_a(0)"
              "a/b/c/reg_b(0)/CLK"
              "a/b/c/reg_c(0)/Q"
              "in(0)"
              "CLK1_WAVEFORM"
            )
            (TO
              "a/b/c/reg_x(0)"
              "a/b/c/reg_y(0)/CLK"
              "a/b/c/reg_z(0)/D"
              "out(0)"
              "CLK2_WAVEFORM"
            )
          )
          (
            (FROM
              "in(2)"
            )
            (TO
              "a/b/c/reg_w(0)/CLK"
            )
          )
        )
        
        (PATH_DELAY (hold negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (setup negedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
        )
        
        (PATH_DELAY (hold posedge 5.00) 
          (
            (FROM
              "a/b/c/reg_c(0)/Q"
              "in(0)"
            )
            (TO
              "a/b/c/reg_z(0)/D"
              "out(0)"
            )
          )
          (
            (FROM
              "a/b/c/reg_d(1)/Q"
            )
            (TO
              "a/b/c/reg_w(2)/D"
            )
          )
        )
        
        (MAX_TRANSITION_TIME 2.10 1.80
          in(0) 
        )
        
        (MAX_TRANSITION_TIME 4.20 3.60
          in(1) 
        )
        
        (LEVEL 1 
          
          (DISABLE 
            (INSTANCE 
              instance1 
              hier1\\\[0\\\]\.hier2\[\*\]\.hier3\\\(0\\\:15\\\)/hier4_with\\\.dot/hier5_with\\\/slash\.leaf\[0\:15\] 
            )
          )
          
          (DISABLE 
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          (DISABLE 
            (INSTANCE 
              instance1 
              instance2 
            )
            (MASTER (CELLTYPE "mylib" "cellc"))
          )
          
          ("label": DISABLE 
            (THRU 
              (
                negedge
                a/in1 
              )
            )
            hold 
          )
          
          (DISABLE 
            (ARC 
              (
                negedge
                a/b/c/d/e/f/g/in1 
              ) 
              (
                anyedge
                a/b/c/d/e/f/g/out 
              )
            )
            setup 
          )
          
          (DISABLE 
            (THRU_ALL 
              (
                posedge
                a/b/c/in1 
              )
              (
                negedge
                a/b/d/in2 
              )
              (
                negedge
                a/b/e/in3 
              )
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("MULTI_CYCLE_LABEL": MULTI_CYCLE 
            (HOLD 1)
            (THRU 
              a/b/c/in1 
            )
          )
          
          (MULTI_CYCLE posedge 
            (SETUP -2 SOURCE)
            (HOLD -1 TARGET)
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          (MULTI_CYCLE 
            (SETUP 3)
            (THRU 
              a/b/c/in1 
            )
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          (PATH_DELAY 5.00 3.00 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU 
              a/b/c/in1 
            )
          )
          
          (PATH_DELAY 5.00 7.00 3.00 3.50 
            (THRU_ALL 
              a/b/c/in1 
              a/b/d/in2 
            )
          )
          
          ("PATH_DELAY_LABEL": PATH_DELAY 5.00 7.00 3.00 3.50 
            (ARC 
              a/b/c/in1  
              a/b/c/out 
            )
            (THRU 
              a/b/c/in1 
            )
          )
          
          (BORROW_LIMIT 6.31
            in(1) 
          )
          
          (BORROW_LIMIT 9.77
            in(2) 
          )
          
          ("CLOCK_DELAY_LABEL": CLOCK_DELAY 
            in_clk 
            ( 
              (INSERTION_DELAY 10.00 11.00 12.00 13.00) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
            ( 
              (SKEW 0.00 1.20)
              a/b/reg_c/clk 
              a/b/reg_d/clk 
            )
            ( 
              (SLEW 0.30 0.40 0.10 0.20) 
            )
          )
          
          (CLOCK_DELAY 
            ( clkbuf in out )
            ( 
              (INSERTION_DELAY 10.00) 
              (SKEW 0.00 1.00)
              (SLEW 0.30 0.40 0.10 0.20) 
              a/b/reg_a/clk 
              a/b/reg_b/clk 
            )
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          TimingSubsetExceptionsExtension
        )
      
      ) // EXCEPTIONS
      
      (EXTENSION "gcftest" 
        TimingSubsetExtension
      )
    
    ) // SUBSET TIMING
    
    (SUBSET PARASITICS 
      
      (ENVIRONMENT 
        
        (EXTERNAL_LOAD 0.68 1.48
          in(1) 
        )
        
        (EXTERNAL_LOAD 9.07 9.72
          in(2) 
        )
        
        (LEVEL 1 
          
          (EXTERNAL_FANOUT 1.65 1.95
            in(1) 
          )
          
          (EXTERNAL_FANOUT 1.66 1.95
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetEnvExtension
        )
      
      ) // ENVIRONMENT
      
      (CONSTRAINTS 
        
        (INTERNAL_LOAD 8.42 8.96
          in(1) 
        )
        
        (INTERNAL_LOAD 0.36 0.57
          in(2) 
        )
        
        (LOAD 0.21 0.57
          in(1) 
        )
        
        (LOAD 6.21 6.73
          in(2) 
        )
        
        (LEVEL 1 
          
          (INTERNAL_FANOUT 5.46 5.61
            in(1) 
          )
          
          (INTERNAL_FANOUT 8.23 8.27
            in(2) 
          )
          
          (FANOUT 0.26 0.64
            in(1) 
          )
          
          (FANOUT 6.16 6.18
            in(2) 
          )
        
        ) // LEVEL 1
        
        (EXTENSION "gcftest" 
          ParasiticsSubsetCnstrExtension
        )
      
      ) // CONSTRAINTS
      
      (EXTENSION "gcftest" 
        ParasiticsSubsetExtension
      )
    
    ) // SUBSET PARASITICS
    
    (SUBSET AREA 
      (PRIMITIVE_AREA 1000.00 1200.00)
      (TOTAL_AREA 1500.00 2000.00)
      
      (LEVEL 1 
        (POROSITY 20.00 50.00)
      
      ) // LEVEL 1
      
      (EXTENSION "gcftest" 
        AreaSubsetExtension
      )
    
    ) // SUBSET AREA
    
    (SUBSET POWER 
      (AVG_CELL_POWER 1.20 1.50)
      
      (AVG_NET_POWER 6.27 7.18
        in(1) 
      )
      
      (AVG_NET_POWER 3.75 4.48
        in(2) 
      )
      
      (EXTENSION "gcftest" 
        PowerSubsetExtension
      )
    
    ) // SUBSET POWER
  
  ) // CELL
  
  (EXTENSION "gcftest" 
    SectionExtension
  )

) // GCF end of file