Subject: Proposed revisions to BUG49; comments?

From: "Mirmak, Michael" <[email-masked]>
Date: Fri, 17 Nov 2000 10:37:10 -0800

IBIS folks,

In today's IBIS Open Forum Meeting, several people made very useful 
suggestions regarding IBISCHK BUG49; thanks to everyone who participated.

To address these comments, I have added a section called "ADDITIONAL NOTES" 
to the original BUG49 proposal.  The updated text is shown below.  
Discussion is welcome.

If the additions resolve the Forum members' concerns, I will file the 
updated text with Bob Ross for discussion and a vote at the next Open 
Forum meeting.

Thanks again!

- Michael Mirmak, Intel Corp.
  [email-masked]

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********************* IBIS GOLDEN PARSER BUG REPORT FORM
*********************
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INSTRUCTIONS

To report a bug in the IBIS golden parser.  Please fill out the top part
of the following form and send the complete form to [email-masked].

A list of reported bugs will be maintained on vhdl.org.

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**

PARSER VERSION NUMBER: 3.2.5

PLATFORM (SPARC, HP700, PC, etc.): HP

OS AND VERSION: HP_UX (B.10.20)

REPORTED BY: Michael Mirmak, Intel Corp.

DATE: November 2, 2000

REVISED: November 17, 2000

DESCRIPTION OF BUG:

"Dangling" models, present but not referenced or used in the file, are not
flagged to the user.  These include [Model]s which are not described in
[Pin], [Model Selector] or [Driver Schedule] sections and also [Submodel]s
which are not referenced by any [Add Submodel] declaration.

Some indication -- most appropriately, a warning -- should be made of the 
lack of reference for these models and model fragments.

An example:

  WARNING (line  xxx) - Model xxx not referenced in [Pin], [Model Selector] 
  or [Driver Schedule] sections.

For Submodels:

  WARNING (line  xxx) - Submodel xxx not referenced by [Add Submodel] 
  keyword.

This bug also applies to DOS32 IBISCHK3 v3.2.5.

ADDITIONAL NOTES:

As pointed out by Mike LaBonte of Cadence, this BUG should also apply to 
[Model]s which are not referenced in a [Series Pin Mapping] section.  
Therefore, a "dangling" [Model] is one which, while syntactically correct, 
is not referenced in [Pin], [Model Selector], [Driver Schedule] or [Series 
Pin Mapping] sections.

Ian Dodd of Cadence raised the point that, for devices such as an FPGA, an 
unreferenced [Model] may be desirable in a user-ready model (such a [Model] 
might represent a available programming option which may or may not be 
implemented after the user configures the device).  In addition, generating 
a message for every instance of an unreferenced [Model] may be unnecessarily

confusing to the user.  

To address the above, the following changed messages are proposed:

For one or more instances of an unreferenced [Model]:

  WARNING (line  xxx) - [Model] zzz not referenced in [Pin],
  [Model Selector], [Driver Schedule] or [Series Pin Mapping] sections.

Only one instance of the above warning message should be generated, for 
the first unreferenced [Model] in the file.  Multiple unreferenced [Model]s
in an IBIS file should NOT generate multiple warning messages.

For Submodels:

  WARNING (line  xxx) - [Submodel] zzz not referenced by [Add Submodel] 
  keyword.

As [Submodel]s should not exist independently of a referencing [Add
Submodel]
keyword, the above message should be generated for EVERY instance of 
an unreferenced [Submodel].

INSERT IBIS FILE DEMONSTRATING THE BUG:
|***********************************************************************
|
[IBIS Ver]       3.2
[File Name]      bug49tst.ibs
[File Rev]       0.0
[Date]           02-November-2000
[Source]         File created from specification
|
[Disclaimer]
    (C) Copyright 2000 Intel Corp.
    All rights reserved
    This model is for demonstration purposes only.
|
|
[Component]      GENERIC_IBIS
[Manufacturer]   Intel Corp.
|
[Package]
|                typ        min        max
R_pkg            6.0mO      5.0mO      7.0mO
L_pkg            5.0nH      2.0nH      8.0nH
C_pkg            1.0pF      0.5pF      1.5pF
|
|
[Pin]     signal_name        model_name    R_pin    L_pin    C_pin
    A1     TestSignal1       TestModel          
    A2     TestSignal2       TestModel          
|
|************************************************************************
|
[Model]          TestModel
Model_type       Output
Polarity         Non-Inverting
Cref = 10.0pF
C_comp                    5.00pF            4.00pF            6.00pF
|
|
[Temperature Range]       27.00             100.00            0.00
[Voltage Range]           3.30V             3.00V             3.60V
[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
  -3.3000      -20.0A           -25.00A             -15.00A
   0.0000       0.0A            -5.00nA              5.00nA
   3.3000       40.00mA          32.00mA             48.00mA 
   6.6000       10.0A            12.0A                8.00A
|
[Pullup]
| voltage     I(typ)              I(min)              I(max)
|
  -3.3000       10.00A              12.00A              8.00A
   0.0000        0.0uA             -0.30uA              0.30uA
   3.3000      -65.00mA            -40.00mA            -80.00mA
   6.6000      -22.00A             -25.00A             -19.00A
|
[Ramp]
| variable       typ                 min                 max
dV/dt_r          0.35/1.6n        0.25/1.8n            0.45/1.5n
dV/dt_f          0.35/1.6n        0.25/1.8n            0.45/1.5n
R_load = 50.000
|

|***************************************************************************
|
[Model]          TestModel2
Model_type       Output
Polarity         Non-Inverting
Cref = 10.0pF
C_comp                    5.00pF            4.00pF            6.00pF
|
|
[Temperature Range]       27.00             100.00            0.00
[Voltage Range]           3.30V             3.00V             3.60V
[Pulldown]
| voltage     I(typ)              I(min)              I(max)
|
  -3.3000      -20.0A           -25.00A             -15.00A
   0.0000       0.0A            -5.00nA              5.00nA
   3.3000       40.00mA          32.00mA             48.00mA 
   6.6000       10.0A            12.0A                8.00A
|
[Pullup]
| voltage     I(typ)              I(min)              I(max)
|
  -3.3000       10.00A              12.00A              8.00A
   0.0000        0.0uA             -0.30uA              0.30uA
   3.3000      -65.00mA            -40.00mA            -80.00mA
   6.6000      -22.00A             -25.00A             -19.00A
|
[Ramp]
| variable       typ                 min                 max
dV/dt_r          0.35/1.6n        0.25/1.8n            0.45/1.5n
dV/dt_f          0.35/1.6n        0.25/1.8n            0.45/1.5n
R_load = 50.000
|
|***************************************************************************
[Submodel] Submodel
Submodel_type  Dynamic_clamp
|
[Power Clamp]
| voltage     I(typ)              I(min)              I(max)
|
  -3.3000       10.00A              12.00A              8.00A
   0.0000        0.0A               0.30A               0.30A
   3.3000        0.00A              0.00A               0.00A
   6.6000        0.00A              0.00A               0.00A

|***************************************************************************
|
[End]
|
|
|Parser 3.2.5 responds with
|
|IBISCHK3 V3.2.5
|
|Checking bug49tst.ibs for IBIS 3.2 Compatibility...
|
|Errors  : 0
|
|File Passed       
|

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******************** BELOW FOR ADMINISTRATION AND TRACKING
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BUG NUMBER:   49

SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT]

PRIORITY: [HIGH, MEDIUM, LOW]

STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG]

FIXED VERSION:

FIXED DATE:

NOTES ON BUG FIX:

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