Subject: 9/14/00 EIA IBIS Open Forum Summit Meeting Minutes

From: [email-masked] (Guy de Burgh)
Date: Wed, 20 Sep 2000 16:20:43 -0700

Date: 9/20/00

SUBJECT: 9/14/00 EIA IBIS Open Forum Summit Meeting Minutes

VOTING MEMBERS AND 2000 PARTICIPANTS LIST:
3Com                           Roy Leventhal
Agilent (EEsof, etc.)          Mark Chang
Ansoft Corporation             (Eric Bracken)
Applied Simulation Technology  Raj Raghuram, Norio Matsui, Fred Balistreri*
Avanti                         Nikolai Bannov
Cadence Design                 Mike LaBonte*, Todd Westerhoff, Ian Dodd*,
                               Donald Telian, Patrick Dos Santos
Cisco Systems                  Syed Huq, Irfan Elahi, John Fisher
Compaq                         [Bob Haller], Peter LaFlamme, Ron Bellomio,
                               Shafier Rahman, Doug Burns
Cypress                        (Rajesh Manapat)
EMC Corporation                Fabrizio Zanella*, Brian Arsenault*,
                               Terry Jernberg*, Alexander Nosovitski*,
                               Elena Gutman*, Shan Haq*
Fairchild Semiconductor        Craig Klem
HyperLynx (& Pads Software)    Matthew Flora, Kellee Crisafulli*, Gene Garat,
                               John Angulo, [Al Davis], Lynne Green*
IBM                            Michael Cohen, Greg Edlund*, Jerry Hayes
Innoveda (Viewlogic Systems)   Chris Rokusek, Guy de Burgh*, Jun Tian,
                               Cary Mandel, Brad Griffin, (Jon Powell)
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Will Hobbs*,
                               Richard Mellitz*, Charles Phares, Meir Nakar,
                               Sigeti Gabi, Tudor Secasiu*, Dave Lorang
LSI Logic                      (Larry Barnes)
Mentor Graphics (& Veribest)   Bob Ross*, Tom Dagostino, Malcolm Ash,
                               Kim Owen, Jean Oudinot, Sherif Hammad,
                               Hazam Hegazy*, Weston Beal, Ken Bakalar
Micron Technology              (Randy Wolff)
Mitsubishi                     Shahab Ahmed, Carleen Murphy, Scott Estrich*
Molex Incorporated             Gus Panella
Motorola                       Ron Werner
National Semiconductor         Milt Schwartz
North East Systems Associates  Edward Sayre*, Tony Sinker, Kathy Breda*
                               Jinhua Chen*
Nortel Networks                Steve Coe, Calvin Trowell, Hassan Ali
Philips Semiconductor          D.C. Sessions, Todd Andersen
  (& VLSI Technology)
Quantic EMC                    (Mike Ventham)
Robinson-Nugent, Inc.          (Alexander Barr)
Siemens AG                     Bernhard Unger, Gerald Bannert
SiQual                         Scott McMorrow, Wis Macomson
Texas Instruments              Stephen Nolan, Ramzi Ammar, Mac McCaughey,
                               Thomas Fisher*, Jean-Claude Perrin,
                               Jean-Yves Oberle
Time Domain Analysis Systems   Dima Smolyansky, Steven Corey
Tyco Electronics (AMP)         (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Werner Rissiek, John Berrie

OTHER PARTICIPANTS IN 2000:
Actel Corp.                    Silvia Montoya
Advansis                       Mikio Kiyono
Aerospatiale Matra CCR         Lionel Dreux, Julien Boullie
Alcatel (Lannion, Bell)        Daniel Peron, Steven Criel
Brocade Communications         Robert Badal
Cereva Networks                Bob Haller*
ECI Telecom                    Daniel Adar
EIA                            Cecilia Fleming
Fraunhofer Institute           Michael Kurten
Jet Propulsion Lab             John Treichlew
KAW                            Shinichi Maeda*
Hewlett Packard                Paul Gregory
RCI                            Chris Rode*
Rockwell Collins               Ron Hau
Signals & Systems Engineering  Tom Hawkins
ST Micorelectronics            Fabrice Boissiere, Pierre Saintot
Sun Microsystems               Victor Chang
Thomson-CSF                    Savenrio Lerose, Pascal Vaslin, Thierry Zak,
                               Sylvie Lasserre
Transfer                       Hans Klos, Wilco Hamhuis
Xilinx, Inc.                   Susan Wu
Independent, Consultant        Hideki Fukuda, Al Davis*

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  October 6, 2000     (916) 356-9200   8-160055         6781387
  October 27, 2000    (916) 356-9200   8-160059         4748326
  November 17, 2000   (916) 356-9200   8-160063         1329512
  December 8, 2000    (916) 356-9200   To be issued
  December 22, 2000   (916) 356-9200   To be issued

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

INTRODUCTIONS AND MEETING QUORUM
Bob Ross welcomed the participants to the IBIS Summit meeting held on
Thursday, September 14, 2000 in the Crowne Plaza Hotel located in Worcester,
Massachusetts at the same time as the PCB Conference East 2000.  Bob thanked
the co-sponsors Cadence Design Systems, HyperLynx, Mentor Graphics, North East
Systems Associates, and the IBIS Users Group and also Kathy Breda for her
work in making the arrangements.  The meeting documents and presentations will
be uploaded at:

  http://www.eda.org/pub/ibis/summits/sep00/

About 29 people from about 15 organizations attended.  Bob introduced the
IBIS officers: Guy de Burgh, Stephen Peters and Mike LaBonte, and also
introduced the former Chair Will Hobbs.  The participants introduced
themselves.  As usual there was good representation from EDA vendors,
semiconductor vendors, model developers (non-commercial and commercial), and
users of EDA tools and IBIS models.

Bob introduced Ed Sayre, Chair of the IBIS Users Group.  Ed stated that the
IBIS East Users Group has not been too active.  This can be interpreted in a
positive manner since there have not been recent controversies with IBIS.
IBIS is well established and respected.  Some of the work initiated by the
Users Group is now being used.  This includes the I/O Buffer Accuracy
Handbook and the Connector Model Specification that is nearing completion.

Ed noted that he still finds most EDA tools hard to use.  He cannot devote the
resources to long term training when he is dealing with short 18 week design
cycles.  Tools need to be simpler to use and have easier interfaces.

The IBIS mission has been accomplished.  Spice models are not the only format.
Behavioral tools are used.  IBIS is less controversial and well-accepted.
However, users still need to push back on manufacturers to get acceptable
models.

Regarding the telecommunications market, Ed notes that many of the telecom
engineers tend to stay in the offices.  Since they are less focused on the
EDA concerns, they need tools that are more user friendly.

Ed is looking for suggestions regarding what future role the the IBIS Users
Group should take.  Ed suggests advancing on-line information accessibility
is one direction.   Kellee Crisafulli suggested having a library of
user-submitted IBIS models.

Bob gave some general business information.  Ansoft has purchased an
ibischk3 parser license.

Bob reported that IBIS is mentioned in "EDA Vendors: Getting Serious About
Signal Integrity" by Gabe Moretti in the September 1, 2000 issue of EDN,
pp. 81-86.

Bob also reported LSI Logic links for Storage Standard Products (under
Symbios IBIS models exist at:

  http://www.lsilogic.com/products/symbios/oem/ibismodels.html

Bob collected and scheduled these opens for discussion or presentations:

Al Davis - IBIS-X at the scheduled round table discussion
Greg Edlund - I/O Buffer Accuracy Handbook Example.

                 PRESENTATIONS AND DISCUSSION TOPICS

The rest of the meeting consisted of presentations and discussions.  These
notes capture some of the content and discussion.  See the uploaded documents
for more detail.

IBIS IN TRANSITION
Bob Ross, Mentor Graphics
Bob Ross reviewed the planned program and noted that the main content
will be on the emerging Connector Specification and on the IBIS Futures
(IBIS-X) development.  There will also be a users experience presentation
and an application of the I/O Buffer Accuracy Report.

Bob reinforced Ed Sayre's previous statements that IBIS serves the industry
well and is a format of choice.  Bob noted that there was considerable
intra-structure surrounding IBIS.  The biggest problem is that IBIS is a fixed
format that is slow to change as technology evolves.  However, IBIS will
continue to serve us well now and in the future.

IBIS is in transition.  The new directions include expanding into the
Connector Specification, issuing an IBIS Version 4.0 with some more
technical and specification detail, and to introduce a future version
of IBIS often designated as "IBIS-X" in terms of a macro language.  IBIS-X
will be compatible with IBIS, but allow faster configurability of IBIS to
support emerging technical needs.  Some plans include a nodal style 
interconnection scheme and elements some level of equation processing.

IBIS AND SI AT 3COM
Roy Leventhal, 3COM (Presented by Mike LaBonte, Cadence)
Mike LaBonte presented some selected material that Roy Leventhal is
presenting at the Cadence Users Group meeting being held the same week as this
meeting.

A number of challenges exist regarding getting good IBIS models that are
accurate and suitable for adding to a corporate data base.  Also challenges
exist for general signal integrity design and training.  While there are
several sources of models from websites and other libraries, the designer is
still responsible for getting the models.  More models are available from
Mike provided update statistics of 17,000 "ibis model" hits versus 59,000
"spice model" hits using the Google search engine.  This compares with only
several hundred IBIS model hits 18 months ago.

The presentation elaborates on the IBIS model sources and on validation and
accuracy.  Mike showed some simulation comparisons.  The original more
simple model provided by the vendor gave some ringing results.  With a more
detailed model that used V-T tables, the results showed better correlation.

An internal signal integrity ISO 9000 process is used.  This process also
includes training.  Currently there are 22 courses available from the
internal web site.  SI could stand for sensitivity and training.  A number
of documents are available to support developing and using IBIS models in
signal integrity and timing analysis.  3Com maintains component libraries
and also links to other IBIS sources.

Practical problems still exist, and there is room for improvement.  Mike
noted that current "default" technology models still tend to be based on
5V supplies.  Semiconductor vendors still need to improve their quality and
response times.

Some discussion occurred during the presentation.  Jinhua Chen asked if the
[Ramp] keyword information was used when V-T tables are given.  Simulators
use the V-T tables and ignore the [Ramp] information.  However, some tools
may still use the [Ramp] information separately for initial routing estimates
for some types of analysis.  Ed Sayre stated that he needed tables which also
provided current for some analysis.

IBIS CONNECTOR SPECIFICATION
Kellee Crisafulli, HyperLynx, and Gus Panella, Molex
Gus Panella showed their contributions to the IBIS Connector Specification
over the past years and then showed a number of changes that the IBIS
Connector Working Group has made from June 2000.

The goals include:

  Incorporating the changes discussed in June 2000
  Ensure that the syntax is not ambiguous
  Improve the syntax descriptions and grammar
  Release the specifaction for a vote by Christmas 2000 time

The document will be available in .doc, .pdf, and .txt format and will include
a Table of Contents for the first two formats.  Some of the the changes that
are temporarily documented in the Revision History section include:

  Making editorial and definition nomenclature changes consistent with IBIS
  Removing [Cn_Z] and adding a suggested Swath expansion section
  Allowing "NC" missing pin [Begin Cn Phy Map] locations
  Requiring an [End ..] for every [Begin ..] keyword
  Supporting explicitly both lumped and distributed matrix sections
  Using multiplers (instead of per-unit-length references) for Cn_Series
    and Cn_Stub sections
  Doing wording cleanup in several sections

The next steps include:

  Considering a more common syntax for the "automap" creation (possibly
    using a "for ... next" style syntax supporting both column and row
    expansion)
  Doing final editing of the Swath section
  Releasing the document to the IBIS Open Forum

The short term goals include:

  Vote for the adoption of Version 1.0 before the end of the year
  Update the examples to support the final syntax and keywords
  Run comparisons with Spice and with the IBIS package model
  Consider a project to convert the .icm syntax back to a Spice format

Some discussion topics during the meeting included whether the case
sensitive portions should be case insensitive, the need for package models
(one idea is to use the "IBIS-X" macro language to wrap the connector around
the die as a package), and the fact that the Connector Specification is
developed as an independent document so that it does not get bogged down
with some existing IBIS convention limitations and can support some specific
requests from the Connector vendors.  Frequency dependent losses are being
deferred because the format debate would take too long to resolve.  However,
there appears to be interest in introducing the [Conductance Matrix] keyword
and to specify R, L, G, and C at several frequencies.

IBIS SWATH MATRIX EXPANSION
Bob Ross, Mentor Graphics
Bob Ross provided some explanation of the newly introduced Swath Matrix
expansion text.  Currently many Spice models are actually provided for just
a smaller set of columns than the entire connector.  This corresponds to the
Swath Matrix option that is proposed.  With Spice connector models, the
section is expected to be centered around the pins of of interest that are
being analyzed.

Bob illustrated this with a diagram that showed two Swaths with an odd and
an even number of columns that could be centered within a larger number of
columns.  The coupling patterns or values for the left-hand and right-hand
swath columns are shown in the diagram to be different.  This could cause some
difference in using the swath matrix with the actual connector for these
columns.  This centering approach also provide the motivation for just
terminating the designated "edge columns" with a characteristic impedance.
The fundamental problem still exists that the nets of interest and
corresponding coupling may extend beyond the columns that are given by the
Swath Matrix.

Bob then showed the assumptions for another approach.  This approach would
expand the center sections of the given Swath Matrix section into a larger
Swath matrix or into the complete connector.  The expansion approach assumes
that the connector coupling pattern is uniform (for MLM), the left-hand and
right-hand Swath matrix patterns are similar to the actual left and right side
coupling patterns of the actual connector, and that the center-most topology
of the Swath Matrix represents the most complete coupling topology for any of
the internal connector pins.  The expansion algorithm assumes that the
center-most topology can be repeated.  Bob then diagramed how this expansion
could occur, by repeating the pattern of the left-hand side, expanding the
center-most topology, and then repeating the right-hand side pattern.

Bob showed some actual [Capacitance Matrix] expansions based on an actual
4 row by 3 column Swath.  He used the Banded_matrix format to show the
capacitive coupling directly.  The numerical examples were actually derived
from an actual Spice model section (with the numerical values changed to
illustrate different left-hand side and right-hand side coupling.  This
Swath Matrix was expanded to a 4 row by 4 column Swath and to a hypothetical
4 row by 500 column connector using an existing utility.  The main points to
note in the examples were:

  The expansion could be done by index manipulation without changing data
    values
  Upper triangle matrix similarities could be exploited.
  A Swath Matrix for an odd number of columns provided a defined center-most
    column location for replicating the center pattern.  This is not a
    a requirement.

Bob then stated that the expansion method could be made more general.  It
could be used for both row and column expansion (as would occur in a packed
pin-grid array) and that it could be also used for expanding into more
columns the Spice netlist source itself.

Ed Sayre suggested that the actual capacitance matrix itself should be
presented to make the Swath Matrix expansion method clearer.

Fred Balistreri raised the question of where the ground is located for the
self capacitance term in the Maxwell capacitance matrix.   Bob thought that
the self capacitance occurred as a mathematical consequence of the format
convention, but he did not have a specific answer for the ground location.

More discussion on the IBIS Connector Specification occurred.  The remaining
work was discussed including developing a more efficient automapping language.
The Working Group is still discussing the syntax.

HTML FORMATTED IBIS MODEL
Stephen Nolan, Texas Instruments
(Presented by Mike LaBonte, Cadence Design Systems)
After breaking for a buffet lunch, Mike LaBonte gave a presentation based on
material from Stephen Nolan.

IBIS models can be presented with additional content and enhanced graphics
in a very easy manner.  IBIS and HTML can be merged such that the enhanced
file still passes ibischk3, parses in EDA tools and can be displayed by
browsers.  Currently most browsers accept "rough" HTML.  They do not require
the .htm or .html file extension and they will accept files with text before
the first "<HTML>" command.

Some suggested changes to the IBIS file format that would allow strictly
compliant HTML displays of IBIS files were given.  The changes would
eliminate the need to view initial "|" comment lines and would support strict
HTML compliance that might be enforced in future browser releases.  Mike and
Stephen plan to work on a BIRD that would allow the the changes.

Mike illustrated the "rough" HTML sample provide by Stephen and also showed
some of the actual embedded HTML tags.  The main idea is to redefine after
the [IBIS Ver] keyword the comment character to be "<".  This allows HTML
commands to be inserted within .ibs files without sacrificing ibischk3
compliance.

The examples showed different fonts under [Disclaimer] for emphasis, some
pinout diagrams, function table and function diagrams, and some data book
graphics explaining the timing test loads.  Bob Ross noted that actual
graphical representations of the I-V and V-T tables can also be given.  Mike
will plan ask Stephen Nolan if the illustration files can be uploaded to
the IBIS FTP site.

AR - Mike LaBonte to get permission to upload Stephen Nolan's sample IBIS
  model that can be displayed using HTML.  [Done]

Discussion occurred during the presentation.  Bob Ross noted that the
proposed IBIS changes include allowing an .ibs.html or .ibis.htm file
extension.  Others suggested that IBIS could be changed to allow the first
character detected in the IBIS file to be defined as a comment character.
Such a change could even be made backwards compatible with earlier versions
of IBIS.  Chris Rode commented that XML is the new direction.  Bob also
noted that the additional graphics are provide by separate .gif files.  At
this time it is not practical to embed these files within the .ibs file.
So these files may not be read into the EDA tool unless there is some method
to name the related files.

IBIS FUTURES OVERVIEW
Mike LaBonte, Cadence Design Systems
Mike LaBonte started the presentation by listing the people who have been
participating in the IBIS Futures Working Group meetings.  The general
discussion themes at the meetings are:

  Format consistency
  Nodal circuit descriptions
  Basic circuit elements, plus tables, equations, triggers, and advanced
    transition lines
  Separation of circuit topology and data
  Dataset correlation beyond min/typ/max
  Support existing IBIS files

Some top-level format discussions have been based on some Connector Working
Group directions (for [Begin ....] and [End ....] syntax and for some
HTML-like constructs for subparameters.

Mike illustrated by using the IBIS [Rac] and [Cac] AC terminator keyword
syntax the concepts of separating circuit topology from data.

The Working group has only dealt briefly with the issue of what lies outside
of the buffers.  How should we deal with die to package and package
parasitics.  Should the new proposal have the same scope as EBD?  Would it
be able to handle frequency dependent RLGC transmission line elements?

Mike concluded the presentation by introducing the main top-level concepts
of the proposed macro language.  These include:

  The language is used inside [Define Model] sections
  There is debate over how much new simulator development should be
    required in the language including:

      Dependent sources controlled by any set of circuit nodes
      Full equations versus simple arithmetic
      General purpose charge and flux elements and the Berkeley Spice
        B element

During the discussion, Ed Sayre commented that there is still interest in
IMIC models from Japanese semiconductor vendors.  Fred Balistreri noted
that IMIC models could be viewed as formatted Spice models.  Arpad Muranyi
noted that the interconnection between blocks was still needed.

CODE BASED MODELS
Tudor Secasiu, Intel
Tudor Secasiu provided the motivation for considering a new format for model
presentation.  Technology is evolving rapidly, frequencies are increasing,
and different tools have different needs ranging from proof of concept to
manufacturability.  Model formats are not keeping up.

Tudor illustrated the current process.  A model card provides the intermediate
step that transforms model parameters into internal equations.  Different
model formats capture pre-defined different equations.  However, these
equations are becoming more refined as technology advances and internal
semiconductor vendor processes are better characterized.

The Code Based Mode approach allows the user (or semiconductor vendor) to
define the model card in terms of actual equations.  These equations can
still use multipling parameters or Taylor series expansions that give the
required accuracy, but still hide proprietary process information.  Tudor
showed an example of user defined equations for a diode.  The output to
simulator engines may be I, V, derivatives, integrals, etc.  This is a
win situation to provide accurate data in a timely manner.

Several things are needed to implement this approach:

  Define a set of functions/equations and methods of encoding with an
    industry standard
  Define a common I/O interface (I, V, C, etc.) and adopt an exiting
    programming language

The Code Based Method can be extended to N-port back box considerations.  The
model can be encoded in a binary format for further protection.  Tudor
concluded by showing some advantages and characteristics of Code Based Models.
What are needed is a definition of a common I/O interface and a real time link
(DLL) of an (encoded) file and also a common set of functions with encoding
capabilities (for example an IBIS extension).

Some concerns were raised in the discussion about detecting the source of
problems in encrypted model and the actual support that might be given for
binaries to maximize portability.  Someone noted that exiting encrypted
binaries can be decrypted and disassembled by existing tools as part of the
process of loading and storing the models into EDA tools.  Even the so-called
encrypted models are not really secure.  

AN ESCAPE HATCH FOR LEADING EDGE SIMULATION
Will Hobbs, Intel
Will Hobbs reinforced some previous comments on the value and success of IBIS.
However, it is not keeping up with technology.  So different circuits must be
modeled at different levels of detail.  Will illustrated this by showing a
different modeling approach for doing analysis from the input of the driver
to the output of the receiver.  This approach is not compatible with IBIS.

Will argued that an application program interface (API) is needed as an
escape hatch.  Its properties are:

  Protect intellectual property
  Be flexible enought to support unforeseen modeling techniques
  Be vendor neutral
  Allow IBIS simulators to meet leading edges needs quickly

An external/executable model interface (XMI) is possible.  Will also discussed
the open model interface (OMI) that is now standardized as IEEE 1499.  He
presented some context diagrams showing how an application would work through
the OMI interface with the model managers and the models themselves.  Multiple
model managers and multiple model instances are allowed.  The model can be
packaged separately or as part of a library.

Will closed by suggesting the steps need for the IBIS committee consider
the API.  However, he commented that the API issue might be handled outside
of the IBIS committee by a different standards group.

IBIS-X SYNTAX FORMAT ISSUES (Ad Hoc discussion)
Arpad Muranyi, Intel
Arpad Muranyi raised a fundamental concern regarding whether a large number
of IBIS-X macro language primitives should be supported for familiarity with
corresponding Spice syntax, or whether some more general purpose syntax should
be supported that makes the syntax variations applicable for all elements.
Should we support having familiar elements, or should we support a more compact
and efficient macro language?  Arpad illustrated this with a resistor example
defined as a two-terminal functional element and also as more general
controlled source element.  In the first case, the resistor could be a
function of its nodes and other elements.  In the second case, a more general
purpose element could allow definition in terms of its own nodes or also other
nodes and parameters.  The first definition would be a redundant subset.
However, support the two terminal format is common in Spice syntax.  This
issue is being discussed with the IBIS Futures Working Group.  We were not
able to proceed much further or get a sense of direction because the group
needed to become familiar with some more "IBIS-X" details available in the next
presentation.

IBIS-X
Al Davis, Consultant
Al Davis gave a more detailed information on the macro language that is
designated "IBIS-X".  He noted that in computer science terms, it is an LL(1)
grammar with LR(1) expressions making the syntax simple and directly dependent
on the first keyword.  Al has begun prototyping the language to help resolve
some of the issues that Arpad Muranyi raised.  (Al had other issues, but he
did not raise them during the presentation.)  This prototype should be
available in November 2000.  It will include a complete macro language
description of IBIS Version 3.2.

Al envisions the general software architecture of IBIS-X to need a "compile"
pass to translate it into internal simulator formats.  This could be done 
automatically.

The elements that are needed by a simulator that would process IBIS-X are:

  The basic ones including piece-wise linear constructs (PWL)
  A two dimensional PWL with time and signal
  A "trigger" to shift time tables

Al presented examples of a number of key points.  IBIS is primarily a data
sheet language.  Al illustrated a structure as a Spice-like description with
expressions.  He compared the existing data format of a Series element with
a structural definition of the [Define Model] Series (pin1 pin2) syntax.

IBIS-X will support conditionals.  Al illustrated the [Define Model]
Series_switch (pin1 pin2 control) syntax that uses a "select (control) and
case statements for [Off] and [On] conditions.  The conditional "if" statement
will also be supported.

A compatible driver element is still being investigated.  Al provide a draft
syntax using a mask for including [Power Clamp] and [Gnd Clamp] tables.

Another aspect is time dependent tables and triggers.  A simple driver that
illustrated using trigger TR and trigger TF to start the rising and falling
transitions based on sensing the V(control) crossing voltages.

Al illustrated other IBIS-X proposed operations and constructs.  An array can
be used to define the [Add Submodel] "Driving", "Non-Driving" and "All" modes.
Al used the [Model Spec] overshoot conditions to illustrate an alarm
operation.  A four pin VCCS (voltage controlled current source) configured
for a [Series_MOSFET] showed the need for 2d tables.  A value expression for
defining the total capacitance including stored charge effects (for example,
from [TTpower] was shown.

Mike LaBonte added during the discussion the power of a correlate statement to
correlate, for example, fast/typical/slow to the min/typ/max columns.  Chris
Rode commented that an alarm failure could be generalized to an event.  Ed
Sayre commented that the Berkeley Spice "B" element provides general current
and voltage relationships with two nodes.  It is an application of Millman's
Theorem stating that this description is sufficient.

Mike commented that another subcommittee might be formed to investigate other
aspects that are not being covered.

I/O BUFFER ACCURACY REPORT EXAMPLE
Greg Edlund, IBM
Greg Edlund responded to the challenge made earlier by Bob Ross that Bob
wanted to see the proposed I/O Buffer Accuracy Report methodology actually
applied to a real part.  Greg stated that he learned some things as a result
of the exercise.  He has produced a large report based on comparing Spice
simulations with laboratory measurements on a known, typical part.

A number of slides from the report were presented.  Greg had particular
difficulty in measuring the effective C_comp.  He also was surprised at the
high correlation values.  While the graphs showed differences, the correlation
numbers were above 90%.  Another metric may give more information.  The report
showed the ESD diodes falling outside the Spice simulations and failing the
envelope metric.  However the simulation and measured transition times
correlated well.  There was some discussion about using an embedded golden
waveform.  It might complicate some simulator algorithms if the defined load
contains transmission line elements.

In the future, Greg plans to work with Purchasing to write model quality into
the specification.  Greg suggests that much of the work could be configured
to run in batch mode.  EDA vendors could also do this.  This study shows that
IBIS can be accurate.  However, there exists the growing need to correlate the
models with physical measurements.

NEXT MEETING:
The next teleconference meeting will be on Friday, October 6, 2000 from
8:00 AM to 10:00 AM.  BIRD64.1 is scheduled for a vote.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Mike LaBonte (978) 262-6496, Fax: (978) 446-6798
            [email-masked]
            Senior Technologist, Cadence Design Systems
            270 Billerica Road
            Chelmsford, MA 01824

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, HyperLynx, Inc.
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
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