Subject: EIA IBIS Summit Meeting Minutes (1/31/00)

From: [email-masked] (Guy de Burgh)
Date: Tue, 8 Feb 2000 11:53:59 -0800

DATE: 2/8/00

SUBJECT: 1/31/00 EIA IBIS Summit Meeting Minutes

VOTING MEMBERS AND 2000 PARTICIPANTS LIST:
3Com                           (Roy Leventhal)
Applied Simulation Technology  Raj Raghuram*, Norio Matsui*, Fred Ballesteri*
Avanti                         Nikolai Bannov*
Cadence Design                 Mike LaBonte*, Todd Westerhoff*, Ian Dodd*,
                               Donald Telian*
Cisco Systems                  Syed Huq*, Irfan Elahi*, John Fisher*
Compaq                         Bob Haller*, Peter LaFlamme*, Ron Bellomio*,
                               Shafiq Rahman*, Doug Burns*
Cypress                        (Rajesh Manapat)
EMC Corporation                (Fabrizio Zanella),
Fairchild Semiconductor        Craig Klem*
H.A.S. Electronics             (Haruny Said)
Agilent (EEsof, etc.)          Mark Chang*
  Hewlett Packard              Paul Gregory*, 
HyperLynx (& Pads Software)    Matthew Flora, Kellee Crisafulli*, Gene Garat*, 
                               John Angulo, Al Davis*, Lynne Green*   
IBM                            Michael Cohen*
Incases                        (Werner Rissiek)
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Will Hobbs*,
                               Richard Mellitz*
LSI Logic                      (Larry Barnes)
Mentor Graphics (& Veribest)   Bob Ross*, Tom Dagostino*, Malcolm Ash*,
                               Kim Owen*
Mitsubishi                     Shahab Ahmed*
Molex Incorporated             Gus Panella*
Motorola                       Ron Werner
National Semiconductor         Milt Schwartz*
North East Systems Associates  Edward Sayre*, Tony Sinker*
NEC                            (Hiroshi Matsumoto)
Nortel Networks                Steve Coe*
Philips Semiconductor          D.C. Sessions*
  (& VLSI Technology)
Quantic EMC                    (Mike Ventham)
Siemens                        Bernhard Unger*
SiQual                         Scott McMorrow*, Wis Macomson*
Texas Instruments              Stephen Nolan*, Ramzi Ammar*, Mac McCaughey*,
                               Thomas Fisher*
Time Domain Analysis Systems   Dima Smolyansky*, Steven Corey* 
Viewlogic Systems              Chris Rokusek, Guy de Burgh*, Jun Tian*, 
                               (Jon Powell)
Via Technologies               (Weber Chuang)

OTHER PARTICIPANTS IN 2000:
Actel Corp.                    Silvia Montoya*
Avanti                         Mikio Kiyono*
Brocade Communications         Robert Badal*
EIA                            (Cecilia Fleming)
Jet Propulsion Lab             John Treichlew*
Rockwell Collins               Ron Hau*
Signals & Systems Engineering  Tom Hawkins*
Sun Microsystems               Victor Chang*
Xilinx, Inc.                   Susan Wu*

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:
  
  Date                Bridge Number    Reservation #    Passcode
  February 25, 2000   (916) 356-9200   4-299297         3855864
  March 17, 2000      (916) 356-9200   4-299298         8432634
  March 31, 2000 - DATE 2000 IBIS Summit Meeting (No Bridge)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
7 days before each Open Forum and meeting minutes out within 7 days after.  
When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

ADDED NOTE AFTER THE MEETING
Congratulations to Syed Huq for having his paper "Effective Signal Integrity
Analysis Using IBIS Models" selected as a Best Paper at DesignCon 2000.

------------------------------------------------------------------------------

INTRODUCTIONS AND MEETING QUORUM
Bob Ross opened the IBIS Summit Meeting held in Santa Clara, California.
About 58 people representing 30 organizations attended throughout the day.
The minutes capture some of the presentation content and related discussions.
Most presentations will be uploaded after they are received at:

  http://www.eda.org/pub/ibis/summits/jun00/

Bob thanked the DesignCon2000 organization for providing the room, the
refreshments and for the booth at the show.  Bob thanked Milt Schwartz and
National Semiconductor for handling the local arrangements including copying
of presentations and also for providing the buffet lunch.  Thank you to
Viewlogic for providing the booth backdrop at the show and to Jon Powell for 
gathering the member company logos.  Finally, thank you to Bob Haller for 
arranging the electrical demonstrations to be discussed later.

Bob R. announced that Molex Incorporated is listed as a new member.

Arpad Muranyi will be giving two days of classes on "Introduction to IBIS 
Models" and " IBIS Modeling Hands-on Experience" at the tutorial short course
"Circuit Simulation and Signal Integrity in Microelectronic Circuits and
Systems" at the University of Arizona on February 14-16 in Scottsdale,
Arizona.

Bob R. mentioned that IEC 62014-1 (IBIS Version 3.2) is scheduled to be 
published in August 2000, but we still need to follow up on its exact status. 

All the participants introduced themselves.  A show of hands indicated that
this group had strong semiconductor vendor and real designer participation,
and moderate EDA vendor participation.

SIMULTANEOUS SWITCHING NOISE (SSN) MODELING
Dr. Bernhard Unger, Siemens AG
Bernhard Unger expanded upon a proposal initially presented at the European
IBIS Summit Meeting in March 1999.  He showed results based on the
two-waveform methodology using HSPICE and IBIS models of the Fairchild
Semiconductor VCX16244 and the LSI Logic BD4 G10 technology.

The enhanced method uses and additional Kssnr multiplier on the pullup table
scaled voltage controlled current source and a kssnf multiplier on the
pulldown table voltage controlled time scaled current sources.  Both
multipliers are a function of the (Vdd-Vss) voltage drop and model the 
feedback on the gate source voltage of the output transistors.  These
multipliers can be derived either by a golden waveform SSO V-T table or 
more directly by Pullup/Pulldown V-I tables as a function of Vdd under a
specified load such as 50 ohms.

Bernhard showed results for 6 switched VCX16244 outputs and 10 switched BD4 
outputs.  These results correlated better than results without the added
multipliers.  However, the best results were obtained when using an additional
prestage capacitance designated Cpre between Vdd and Vss.  Bernhard showed
comparisons that were nearly equivalent to Spice simulations for most of the
test cases.  One test case for noise on a quite buffer showed same magnitude
as the reference Spice simulation, but did not overlay as well as the other
tests.

Bernhard concluded that while the results are good, more investigations on 
the valid range and accuracy of the proposed model would be valuable.

Arpad Muranyi questioned why C_comp was split into two parts, and Bernhard
responded that he split C_comp for Spice simulation convergence improvement.
We discussed further the splitting C_comp per pending BIRD65.  Several
attendees expressed interest in this general approach to SSN modeling.

DESIGNCON2000 IBIS SUMMIT BOOTH DEMO
Bob Haller, Compaq
Bob Haller stated that the booth number 1039 is being setup. It is a neutral
meeting place for IBIS members.  Logos of many member companies are being
displayed (thanks to Jon Powell).  A test board for connector measurements
is being displayed along with the accuracy test board.  Bob thanked Agilent
Technology for loaning the oscilloscope.

The connector demonstration will show measurements:

  Impedance
  Crosstalk
    Single active technique
    Spreadsheet
  Propagation delay
  SSO (not demonstrated)

This demonstration is a complement to the draft IBIS Connector Specification
that will be on display to deal with an important industrial issue.

BRIEF HISTORY OF THE IBIS COMMITTEE (Ad Hoc)
Bob Ross displayed the list of contributors for June 1993 IBIS Version 1.0 
that exists in the document.

Many of the original founding companies are still active in the IBIS Open
Forum, but with different names due to acquisitions and mergers.  Among the
current attendees where the founding members and former IBIS Chairs Donald
Telian and Will Hobbs.  Arpad Muranyi (not listed) and Kellee Crisafulli were
also active in the "early" days.

The specification lists names and "telephone" numbers.  Email was just
starting to be used.  Bob noted that while Jon Powell's company name has
changed about four times, his telephone number remains the same.  We have
continued since the very beginning to conduct teleconference meetings about
every three weeks.  Initially the minutes were distributed by surface mail
and FAX.  In the later years, we made use of e-mail lists and websites.

The committee has grown to over 30 member companies with much broader user
and semiconductor company representation than just Intel.  The Specification
has grown considerably, but many new important issue now exist.  The new
question is: what will the IBIS Committee and technical interaction be like
in the next 7 and 1/2 years?

IBIS CONNECTOR SPECIFICATION
Gus Panella, Molex
Gus Panella briefly introduced the pending IBIS Connector Specification
and mentioned a few specific details in the document.  

Briefly, it support many different types of connector modeling methods and
all types of connectors.  For example the following are supported:

  Differential and unbalanced signaling
  Single line models (uncoupled)
  Multiline models (coupled)
  Cascaded models
  Angled connectors
  Cross connected pins
  Board to board
  Board to cable

Furthermore, it has the following capabilities:

  Swath matrix to allow pin expansion without matrix expansion,
  Simulator compatible and consistent node mapping and parameter definition,
  More than one model can be described in just a few lines.

Gus discussed the cascaded sections and showed that by changing just one
section, different connector models can be produced to support connections
to boards with different thicknesses.

Third party vendors can add value in several areas including software to
extract models from geometry, model confirmation service, etc.

Gus then listed an number of activities for acceptance and promotion of the
connector specification.  These included a golden parser, a possible BNF
description, reference models, accuracy methodology documentation, and
general publicity.

Upon questioning, Gus indicated that the connector proposal used the Maxwell
matrix format.

Bob Ross and Kellee Crisafulli joined Gus to discuss and attempt to resolve
a few of the comments.  After discussions and group votes, we agreed to modify
the proposal in the following ways:

  The extension .ibiscnn will be changed to .icm for "IBIS Connector Model"
    since there might be cases under DOS representation under Windows where
    the extension is reduced to 3 characters

  The mixed 80 characters and 120 characters per line for "comment" versus
    technical lines was resolved to be a 120 character limit throughout.  
    Longer matrix lines can still be wrapped, so no data is lost.  The 120
    character limit still allows printing the model in landscape mode for
    visual inspection.  However, keeping lines less than 80 characters is
    still recommended, if possible, as good practice.

  The keywords [Email] and [Website] are to be replaced by one [Support]
    keyword provides a common location for contacting the source.  This avoids
    specific syntax rules and also allows for new methods that could emerge.

  We were divided regarding the need and usage of [Redistribution] keyword 
    and will take up this issue at a later time.  The connector companies
    want this keyword.

Gus and Bob had other items that needed to be discussed.  However, Bob 
suggested that we continue the discussion on the reflector and at future
meetings so we could move on to other items on the Agenda.

USING STATISTICAL METHODS TO CHARACTERIZE RECEIVERS TO DETERMINE THE 
APPLICABILITY OF RECEIVER MODELING STANDARDIZATION
Richard Mellitz, Intel
As part of the general topic of behavioral input characterization Richard
Mellitz defined a characterization process and showed some results.

The basic problem is to improve timing simulation prediction over the "time
to threshold" technique and also to determine of the characterization is
feasible for a given receiver.  Richard than described steps in the process
to do this.

Richard suggested and illustrated these stimuli and discussed what they
would be testing:

  Slew Rate Case
    Slew rate
    Overdrive
    Threshold sensitivity
    
  Shelf Case
    Monotonic sensitivity
    Overdrive
    Threshold sensitivity
    Define threshold region of uncertainty

  Ringback Case
    Ringback sensitivity
    Notch discrimination

  Inflection Case
    Monotonic sensitivity
    Overdrive
    Threshold sensitivity
    Define threshold region of uncertainty

  Settling Case
    Settling voltage
    Overdrive

  Frequency Case
    Frequency noise sensitivity
    Noise amplitude rejection
    Power supply noise rejection
    Vref noise sensitivity

Overlaying waveform and three-dimension plots based on Monte Carlo simulations
were presented to illustrate these effects and to suggest some conclusions
regarding some receivers:

  Have predictable delay and performance
  Have undesirable areas of operation, i.e., metastability, etc.
  Need specification margins to assure performance
  Are more sensitive to power supply noise

Richard concluded by raising these questions:

  What is a necessary and sufficient set of input waveforms?
  What type of performance need to be modeled?
    What is delay as a function of receiver parameters?
    Where is a safe region of oxide wear out?
    When should a receiver be considered unpredictable?

A number of questions and much discussion followed this presentation.

BEHAVIORAL RECEIVER MODELING
Donald Telian, Cadence Design Systems
After the delicious buffet lunch hosted by National Semiconductor, Donald
Telian commented that this is a major improvement from the early days of
sandwiches and chips.

Donald introduced the topic by showing how design methodology has evolved:

  Use terminations (mid-1980s)
  Driver scaling and tuning (early 1990s setting the stage for IBIS and for
    tools allowing topology optimization)
  Now - more detailed receiver modeling

Behavioral receivers are needed for simplification, performance, and design
optimization.  Donald elaborated on these points and summarized that a
receiver can be tuned just like we are used to doing with the driver and
interconnect.

Donald discussed three general approaches to receiver modeling:

  Silicon-level Spice description (slow and proprietary)
  Pre-configured behavioral description (has a defined structure, and imitates
    only one thing, and can be too limiting)
  Nodal behavioral description (models receivers characteristics and 
    adaptable to arbitrary behaviors)

Donald then outlined a nodal implementation dubbed as the Digital Universal 
Behavioral (DUB) Receiver Model.  He showed and illustrated a block diagram
consisting of these blocks:

  #1: Low Pass Filter - reject certain pulse spikes
  #2: Switching Function - receivers basic transfer function
  #5: Intrinsic Delay - delay for fastest edge
  #3: Edge Rate Detection - derivative of input signal effects delay
  #4: Delay Adder - dynamically adjusts circuit delay based on #3

The components to implement this include:

  Nodal language
  G (VCCS) and E (VCVS)
  Real-time adaptive delay line
  Subcircuit nesting and random node printing

Donald then showed some speed and accuracy comparisons with Spice models and
indicated good performance.  More work could have yielded even higher
accuracy.

He recommends that if IBIS implements behavioral receivers, a nodal language
be used to deal with unique situations.  He stated that the compelling
application that prompted the need for IBIS drivers was the PCI bus and the
Pentium processor.  Donald concluded by asking if there is a compelling
application that requires behavioral receivers.

D.C. Sessions responded by mentioning the double data rate (DDR) DRAM model
needs, and Arpad Muranyi mentioned the PCI 133.

FUTURE OF IBIS
Bob Ross introduced the next segment of the meeting.  We have already heard
some specific proposals regarding SSN, connector modeling and input modeling.
Regarding future directions, a number of overlapping proposals and suggestions
have been issued.  Bob then listed some options based on recent e-mail 
reflector comments:

  IBIS-X (Stephen Peters)
  API (Will Hobbs)
  BIRDxxx (not yet issued, Arpad Muranyi)
  Equations (Arpad Muranyi)
  Structures (Al Davis)
  Macromodels (Paul Franzon)
  Linkage Syntax in IBIS (Scott McMorrow)
  Enhanced IBIS for Inputs (D.C. Sessions)

Also, Bob showed that we could also have links:

  Spice
  IMIC
  S-parameters
  EDIF
  VHDL-A or Verilog
  C
  etc.

Some of the proposals are discussed in the remaining presentations.

MACRO EXTENSIONS FOR IBIS
Al Davis, HyperLynx
Al Davis proposed that with macro extensions to IBIS we would not need so
many BIRDS for advances.  Macro extensions define the circuit topology,
parameterize it, and also provides a library.  Other options would be Spice
IMIC, and VHDL or Verilog.

Al then illustrated providing macro extension for several examples including
a parallel and series terminator.  The approach is compatible with such IBIS
advances as Waveform, [Pullup] and [Pulldown] interactions; Series Switch
[On] and [Off]; Correlation (typ, min, max) and Attachments ([Add Submodel],
[Driver Schedule]).  He illustrated this with a driver example.

Al proposed these components:

  Spice R, L, C, V, I, E, G
  Some Spice extras such as voltage controlled conductance, resistance and
    capacitance (vcg, vcr, vccap)
  Non-Spice attributes for driver, trigger, and alarm
  Programming for assert, define, export, if, inherit, local, and select

He concluded that a new section [Define Model] could be used to describe the
topology of [Model] and [Submodel].

Al stated that a draft language reference manual as attached to his
presentation.

FUTURE DIRECTIONS FOR IBIS
Arpad Muranyi, Intel
Arpad Muranyi started the discussion by commenting on the IBIS reflector
thread he started in December 1999 on what people thought should be done with
the IBIS Specification.  The results are summarized as an Appendix to the
presentation.

Arpad listed these problems:

  The current IBIS syntax is inflexible because the majority of the keywords
  are based on (individual) assumptions and usage rules

  Connectivity between die and package is also based on assumptions and usage
  rules

  This type of a syntax slows down growth and limits the possibility of 
  adding new features quickly

  A specification with such syntax becomes unmanageable

The solution is a new syntax that is:

  scalable (two .. N-terminal black boxes)
  general purpose (anything in the black box)
  nodal (allow arbitrary connections between black boxes and between a
    collection of black boxes and the outside world)

Arpad showed a block diagram that had die interconnect circuitry between  the
package and the die.  This diagram illustrated the concept behind an
unreleased BIRDxxx proposal.  Arpad listed these advantages:

  Supports current IBIS format (backward compatibility)
  Supports IMIC format
  Supports full Spice format
  Allows any level of abstraction available for flexibility, accuracy, and
    security (IP protection)

To implement this, he uses a Spice syntax with some behavioral features.
However, the borderline between just "model" and "just data" becomes fuzzy.

Arpad proposes taking action by considering and adopting one of these options:

  A Spice-like nodal syntax
  An object oriented programming language style syntax
  XML language

Ian Dodd stated that currently the EBD structure is a subset.  D.C. Sessions
commented that the package interconnect is becoming the dominant design issue.
Also, other languages such as VHDL-AMS and Verilog should be considered.  Don
Telian suggested encryption as a possible solution.

MODELING APPROACHES: TABLES VERSUS EQUATIONS
Dr. Lynne Green, HyperLynx
Lynne Green stated the problem that more points and more tables can produce
very large files.  As features and details are added, libraries of models
can consume significant memory and also slow down loading and simulation.
Lynne illustrated this with a worst case model.  On the other hand, a few
small tables load, search, and simulate rapidly.  Tables can grow, but
equations are always smaller and faster.

Lynne cited a University of Washington study regarding a power FET model.
Using equations improved storage, speed and accuracy.

Lynne listed a number of specific benefits for using equations.  She proposed
more university investigation on:

  Small equation set
  Mix tables and equations
  parser for equations
  file size impact
  simulation impact

DISCUSSION - THE FUTURE OF IBIS: THE IBIS-X PROPOSAL
Stephen Peters, Intel
Stephen Peters outlined the specific IBIS-X proposal by citing these
guidelines:

  Retain features that support board level simulators and electrical rule
    driven routers

  Add features that support circuit type simulators

  Provide a path for external models (i.e., API Interface)

Stephen showed and illustrated the outline consisting of these sections"

  File Header
  Component
  Model

One important addition is to introduce [Begin Model].  It supports much of 
the existing IBIS [Model] keywords plus some proposed BIRD62.2 and BIRD63.2
input details.

Also Stephen presented some port types that would be listed in a new [Port
List] keyword:

  primary_io      primary I/O pin
  pullup_ref      power connection pins
  pulldown_ref
  pwrclamp_ref
  gndclamp_ref
  rcvr_ref        
  gnd             reference pin
  ctl             a digital (I/O) control pin
  analog          an analog control pin
  stim_in         an external stimulus (not a component pin)
  receiver_out    output of a receiver (not a component pin)

The models section also supports nodal descriptions with conventional 
Spice-like syntax for resistors, inductors, capacitors and voltage and
current sources.  It also supports an Sxxx element for equations or tables
for three terminal devices and Xxxx for attaching ports of submodels.

Questions and discussion occurred on various aspects.  Al Davis volunteered
to work with Stephen and Arpad Muranyi to come up with a unified proposal.

Will Hobbs proposed a trap door escape path using an application programmable
interface (API).  D.C. Sessions mentioned some new language alternatives.
One concern is that the encryption may be platform independent.

CLOSING REMARKS
Bob Ross thanked Milt Schwartz and National Semiconductor for handling
the local arrangements and providing the excellent lunch.  Bob noted that
the next IBIS Summit meeting is scheduled on Friday, March 31 in Paris,
France at the end of the DATE2000 Conference.  

Also Bob set the next teleconference meeting on Friday, February 25, 2000 
and stated that BIRD62.2 and BIRD63.2 are scheduled for a vote.

Several people met briefly after the meeting to discuss the upcoming JEDEC/
IBIS working group meeting scheduled for Thursday, February 3, 2000.

NEXT MEETING:
The next teleconference meeting will be on Friday, February 25, 2000 from
8:00 AM to 10:00 AM.  BIRD62.2 and BIRD63.2 are scheduled for voting.

------------------------------------------------------------------------------

              JEDEC/IBIS WORKING GROUP MEETING - BRIEF NOTES

Date/Time:  Thursday, February 3, 2000, 1:00 PM - 5:00 PM
Location/Host: Philips Semiconductor, San Jose, CA, D.C. Sessions

Title:  IBIS as a Specification Language

Attendees:

  IBIS:  Bob Ross, Mentor Graphics
         Kellee Crisafulli, HyperLynx
         Fred Ballesteri, Applied Simulation Technology
         Mike LaBonte, Cadence Design Systems
         Richard Mellitz, Intel
         Arpad Muranyi, Intel

  JEDEC: D.C. Sessions, Philips Semiconductor (Chair JC-16)
         Gil Russell, Infineon Technologies (Chair., JC-16.2)
         Howard Sussman, Sanyo

Driving Force:  Advances in DDR DRAMS

Specification Needs (more clarification needed):

  1. Differential Output Coupling at the Buffer to Pad level 
  2. A delta C_comp limit for buffers at the component level
  3. SSTL-2 Input enhancements (BIRD62.2, BIRD63.2)

Application Needs:

  1. Relative Pad Delay (Skew in delay to pad)
  2. Return Path details (possibly using Dr. Unger's SSN approach above)
  3. Input Modeling (initially BIRD62.2, BIRD62.3

An IBIS Working Group on consisting of (at least) Arpad Muranyi, Kellee
Crisafulli, Mike LaBonte, D.C. Sessions and Richard Mellitz will work on
these issues and generate proposals.

Next JEDEC and JC-16 and JC-42 Meetings:
  Friday, February 4, San Jose, California
    Report on the JEDEC/IBIS meeting and on future work

  Approximately March 7, 2000, Atlanta, Georgia

==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave. 
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Viewlogic Systems
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Scientist, Viewlogic Systems
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Signal Integrity Engineer, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Senior Engineer, HyperLynx, Inc.
            114715 N.E. 95th Street
            Redmond, WA 98052
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org/eig/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================