Subject: BIRD 65.2

From: "Muranyi, Arpad" <[email-masked]>
Date: Fri, 2 Feb 2001 13:28:28 -0800

****************************************************************************
**
****************************************************************************
**

BIRD ID#:        65.2
ISSUE TITLE:     C_comp Refinements
REQUESTER:       Arpad Muranyi, Intel
DATE SUBMITTED:  10-25-99, 12-12-2000, 2-2-2001
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

****************************************************************************
**
****************************************************************************
**

STATEMENT OF THE ISSUE:

Currently, the IBIS specification (v3.2) uses a single constant value for
describing the total die capacitance as seen at the pad.  This value is
given
by the subparameter C_comp under the [Model] keyword.  The specification
does
not mention how this capacitance is distributed between the power and ground
references, or how it should be connected to the circuit.

****************************************************************************
**

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Four new subparameters shall be introduced in the IBIS specification under
the [Model] keyword to provide means for a more detailed description for the
die capacitance.  These new subparameters, C_comp_pullup, C_comp_pulldown,
C_comp_power, and C_comp_gnd are associated with the corresponding voltage
reference keywords, [Pullup Reference], [Pulldown Reference], [Power Clamp
Reference], and [GND Clamp Reference], respectively.  This mechanism allows
the association of a specific capacitance between the I/O node and the four
possible supply nodes without disturbing the submodel syntax.

The syntax of these four new subparameters are identical to the existing
C_comp subparameter.

|===========================================================================
==
|     Keyword:  [Model] 
|    Required:  Yes.
| Description:  Used to define a model, and its attributes.
|  Sub-Params:  Model_type, Polarity, Enable, Vinl, Vinh, C_comp,
|**             C_comp_pullup, C_comp_pulldown, C_comp_power, and
|**             C_comp_gnd Vmeas, Cref, Rref, Vref
| Usage Rules:  Each model type must begin with the keyword [Model].  The
|               model name must match the one that is listed under a [Pin],
|               [Model Selector] or [Series Pin Mapping] keyword and must
not
|               contain more than 20 characters.  A .ibs file must contain
|               enough [Model] keywords to cover all of the model names
|               specified under the [Pin], [Model Selector] and [Series Pin
|               Mapping] keywords, except for those model names that use
|               reserved words (POWER, GND and NC).
|
|               Model_type must be one of the following:
|
|               Input, Output, I/O, 3-state, Open_drain, I/O_open_drain,
|               Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|               Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, Terminator,
|               Series, and Series_switch.
|
|               Special usage rules apply to the following.  Some
definitions
|               are included for clarification:
|
|               Input              These model types must have Vinl and Vinh
|               I/O                defined.  If they are not defined, the
|               I/O_open_drain     parser issues a warning and the default
|               I/O_open_sink      values of Vinl = 0.8 V and Vinh = 2.0 V
are
|               I/O_open_source    assumed.
|
|               Input_ECL          These model types must have Vinl and Vinh
|               I/O_ECL            defined.  If they are not defined, the
|                                  parser issues a warning and the default
|                                  values of Vinl = -1.475 V and Vinh =
|                                  -1.165 V are assumed.
|
|               Terminator         This model type is an input-only model
|                                  that can have analog loading effects on
the
|                                  circuit being simulated but has no
digital
|                                  logic thresholds.  Examples of
Terminators
|                                  are: capacitors, termination diodes, and
|                                  pullup resistors.
|
|               Output             This model type indicates that an output
|                                  always sources and/or sinks current and
|                                  cannot be disabled.
|
|               3-state            This model type indicates that an output
|                                  can be disabled, i.e. put into a high
|                                  impedance state.
|
|               Open_sink          These model types indicate that the
output
|               Open_drain         has an OPEN side (do not use the [Pullup]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SINKS current.  Open_drain model
|                                  type is retained for backward
|                                  compatibility.
|
|               Open_source        This model type indicates that the output
|                                  has an OPEN side (do not use the
[Pulldown]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SOURCES current.
|
|               Input_ECL          These model types specify that the model
|               Output_ECL         represents an ECL type logic that follows
|               I/O_ECL            different conventions for the [Pulldown]
|               3-state_ECL        keyword.
|
|               Series             This model type is for series models that
|                                  can be described by [R Series], [L
Series],
|                                  [Rl Series], [C Series], [Lc Series],
|                                  [Rc Series], [Series Current] and [Series
|                                  MOSFET] keywords
|                                 
|               Series_switch      This model type is for series switch
|                                  models that can be described by [On],
|                                  [Off], [R Series], [L Series], [Rl
Series],  
|                                  [C Series], [Lc Series], [Rc Series],
|                                  [Series Current] and [Series MOSFET]
|                                  keywords
|
|**             The Model_type subparameter is required.  The C_comp
|**             subparameter is only required if C_comp_pullup,
|**             C_comp_pulldown, C_comp_power, and C_comp_gnd are not
|***            present.  If the C_comp subparameter is not present at least
|***            one of the C_comp_pullup, C_comp_pulldown, C_comp_power, and
|***            C_comp_gnd subparameters is required.  It is not illegal 
|***            to define all five of these subparameters, but in that case
|***            the simulator tool will have to make a decision whether 
|***            to use the old C_comp subparameter or the new C_comp_*
|***            subparameters.  Under no circumstances should all five
|***            subparameters be used simultaneously.
|
|               The Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, and
Vref
|*              subparameters are optional.  C_comp* define the silicon die
|*              capacitance.  Thse values should not include the capacitance
|*              of the package.  C_comp* are allowed to use "NA" for the min
|               and max values only.  The Polarity subparameter can be
|               defined as either Non-Inverting or Inverting, and the Enable
|               subparameter can be defined as either Active-High or
|               Active-Low.
|
|               The Cref and Rref subparameters correspond to the test load
|               that the semiconductor vendor uses when specifying the
|               propagation delay and/or output switching time of the model.
|               The Vmeas subparameter is the reference voltage level that
the
|               semiconductor vendor uses for the model.  Include Cref,
Rref,
|               Vref, and Vmeas information to facilitate board-level timing
|               simulation.  The assumed connections for Cref, Rref, and
Vref
|               are shown in the following diagram:
|
|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     === Cref
|                           |_________|      |
|                                            |
|                                           GND
|
| Other Notes:  A complete [Model] description normally contains the
following
|               keywords:  [Voltage Range], [Pullup], [Pulldown], [GND
Clamp],
|               [POWER Clamp], and [Ramp].  A Terminator model uses one or
|               more of the [Rgnd], [Rpower], [Rac], and [Cac].  However,
some
|               models may have only a subset of these keywords.  For
example,
|               an input structure normally only needs the [Voltage Range],
|               [GND Clamp], and possibly the [POWER Clamp] keywords.  If
one
|               or more of [Rgnd], [Rpower], [Rac], and [Cac] keywords are
|               used, then the Model_type must be Terminator.
|---------------------------------------------------------------------------
--
| Signals       CLK1, CLK2,...         | Optional signal list, if desired
[Model]         Clockbuffer
Model_type      I/O
Polarity        Non-Inverting
Enable          Active-High
Vinl = 0.8V                            | input logic "low" DC voltage, if
any
Vinh = 2.0V                            | input logic "high" DC voltage, if
any
Vmeas = 1.5V              | Reference voltage for timing measurements
Cref = 50pF               | Timing specification test load capacitance value
Rref = 500                | Timing specification test load resistance value
Vref = 0                  | Timing specification test load voltage
| variable      typ             min             max
C_comp          12.0pF          10.0pF          15.0pF
|
|===========================================================================
==
|
[Model]         Clockbuffer
Model_type      I/O
Vinl = 0.8V                            | input logic "low" DC voltage, if
any
Vinh = 2.0V                            | input logic "high" DC voltage, if
any
|
| variable      typ             min             max
C_comp_pullup   3.0pF           2.5pF           3.5pF
C_comp_pulldown 2.0pF           1.5pF           2.5pF
C_comp_power    1.0pF           0.5pF           1.5pF
C_comp_gnd      1.0pF           0.5pF           1.5pF
|
****************************************************************************
**

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Problem statement

The single (constant) C_comp value of the current IBIS specification (v3.2)
does not provide enough information for the simulator to accurately simulate
high speed signals and/or ground and supply noise.

In order to simulate the signal current return path and/or supply rail noise
(GND bounce and/or Vcc droop) accurately, a model needs to provide more
detail on the distribution of the total die capacitance between the I/O pad,
power and ground references.  This BIRD attempts to provide the means for
incorporating such information in a model.

The existing C_comp subparameter does not specify how it should be connected
between the I/O pad and the supply rails.  Most naturally it will end up
getting connected to the I/O node and ground.  However, since it not only
represents the capacitance of the pulldown device, but also the capacitance
of
the pullup device, one should split it between the I/O pin and ground, and
the
I/O pin and power rails.  One can easily see that this configuration forms a
series combination of two capacitances between power and ground.
Simulations
show a significant difference in the waveforms for the distributed or lumped
capacitance when power and ground nodes of the die are connected through the
package parasitics to the ideal power source(s).

Possible solutions

1)  Specify splitting factor coefficients
2)  Use a new subparameter under each voltage reference keyword
3)  Use a new subparameter under each I-V curve
4)  Use four new subparameters under the [Model] keyword (as presented in
    this BIRD).

****************************************************************************
**

ANY OTHER BACKGROUND INFORMATION:

Changed the names for the four C_comp* parameters as requested in the 
12-08-2000 IBIS Open Forum Teleconference meeting.  Added the next 
paragraph.

Transistors (consequently buffers) show different parasitic capacitance when
turned on or off.  Additional mechanisms need to be added to the IBIS 
specification to account for these variations.

The voltage dependency of the die capacitance should also be addressed at
some
point. (Use typ., min., max, capacitance vs. voltage tables instead of
single
values)?

****************************************************************************
**

---

From: Al Davis <[email-masked]>
Date: Wed, 7 Feb 2001 10:55:37 -0800

(Most of this message is a repeat, because the issues have not been 
addressed.)

I have some questions and reservations on this.  To summarize, although 
I agree that such a thing is needed, this proposal does not solve the 
problem adequately and has the potential for introducing problems that 
have not been considered.  Also, the problem it intends to solve 
becomes a non-issue once IBIS-X is completed.

The first question is how difficult it is to implement.  Ordinarily, I 
would say that it is necessary to prove it with a prototype, but it is 
a simple topology change, so it would be no worse than the existing 
C_comp.  Incidentally, the C_comp as we know it is rarely implemented 
correctly for driving models.  It is very difficult to do correctly.  
The implementations tend to be very good for non-driving models, where 
it is just a simple capacitor.  In any case, it is no worse than what 
we have so I am satisfied on this point.

Still, testing is a problem.  How do you measure it?  How do you 
validate that the measured data actually relates to reality?  Before 
approval of this bird, I would like to see a description of a procedure 
for measuring it, and a procedure for validating that the measured data 
is actually correct and useful.  These procedures should be tried on a 
prototype.

The purpose is stated to be information on how the capacitance is 
distributed over the 4 ground/power nodes.  Another way to look at it 
is how the current in the capacitance is distributed.  OK.  Now back 
up.  We have pullup/pulldown and the clamps for the DC conditions.  The 
proposed c_comp's are the dynamic parts.  Existing models usually do 
not model the split of these correctly.  The pullup and power clamp are 
sort of in parallel, so the measurement is usually to measure the 
clamps in input or tri-state mode, and the pullup/pulldown in driving 
mode, by measuring a total and subtracting off the clamps.  This often 
leads to the pullup/pulldown showing strange bahavior when it is masked 
by the clamps, because the subtraction magnifies the errors.  In any 
case, the current path is not necessarily as intended.  The standard 
provides the mechanism to properly model the current paths, but most 
models do not.  They arbitrarily mix them.

Given that most models do not get the DC split correct, what justifies 
even trying for the dynamic part?

The next issue is that this capacitance is strongly nonlinear.  
Measuring it in the various states produces very different results.  
Even then, there is no hint at what they do during the transition, 
other than that the wave tables include the effect.  The wave tables do 
not provide information on how that current is distributed to the 4
power/ground nodes, and possibly also to other connection nodes 
including input and enable.

The nonlinear nature of this capacitance is significant in the 
development of the simulator algorithms.  Some actual models will only 
work accurately when the capacitance is treated as nonlinear.

Part of this capacitance is already in the standard as transit time.  
The [TT*] parameters are essentially equivalent to the C_comp_power and 
C_comp_ground parts, complete with the nonlinear component.  Thus, part 
of what this bird proposes is already available.  (OK -- the bird asks 
for the linear part.)  Do you have any examples of actual models that 
use these parameters?  with test data showing the quality of 
correlation to the real device?  How many simulators support it fully?  
It has been in the standard for a long time.

Considering the number of unanswered questions, and that this 
functionality and much more will be available in IBIS-X, I think it is 
best not to rush into this.

So, Arpad, you should prototype this in IBIS-X (trivial) , and also 
prototype a measurement system for it in IBIS-X (not so trivial).  This 
will validate both this bird and IBIS-X.  The rest of us should wait 
for the answer.

Note to readers not familiar with IBIS-X:  This is a proposed future 
IBIS based on a macro language.  It is fully backward compatible with 
IBIS as we know it, and provides the capability to add extensions like 
this one easily.  Arpad and I are both on the sub-committee that is 
working on it.  A prototype implementation of IBIS-X is being built, 
and a partial one (incomplete work in progress) is available for review 
to the committee and to those interested.

The change in wording of the "required" section is an improvement, but 
it still needs work.

How about:

Either the C_comp parameter or all four of C_comp_pullup, 
C_comp_pulldown, C_comp_power, and C_comp_gnd are required.  If C_comp 
is provided, the others are not allowed.

---

From: "Baikuan Wang" <[email-masked]>
Date: Thu, 8 Feb 2001 10:14:18 -0800

Hi, IBIS exports,

Regarding V(t) curve, the following circuit is given including
R_dut, L_dut and C_dut. My question is:
The rising/falling waveform refers to Voltage at the node
between C_dut and L_fixture. Am I right? Can you comment?
Thanks.

Brian
Sigity, Inc.

|
|                      PACKAGE            |   TEST FIXTURE
|       _________                         |
|      |  DUT    |   L_dut   R_dut        | L_fixture  R_fixture
|      |  die    |---@@@@@--/\/\/\--o-----|--@@@@---o---/\/\/\-----
V_fixture
|      |_________|                  |     |         |
|                                   |     |         |
|                                   |     |         |
|                            C_dut ===    |        === C_fixture
|                                   |     |         |
|                                   |     |         |
|                                  GND    |        GND
|

---

From: Bob Ross <[email-masked]>
Date: Thu, 08 Feb 2001 10:46:34 -0800

Brian:

You are correct.

Bob Ross
Mentor Graphics