Subject: Re: PCI and IBIS

From: "Gregory R Edlund" <[email-masked]>
Date: Fri, 2 Feb 2001 08:58:18 -0600

Syed,

I asked this question two years ago.  Here are the answers I got.

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email-masked]

To All:

The IBIS Version 3.1 format could theoretically handle this
multiple test load situation by using the [Model Selector]
keyword to reference individual [Model] keywords containing
the same information except for the individually specified
test loads.  However, it is likely that the user would to
manually manage the analysis for testing the design corners.

Bob Ross
Interconnectix/Mentor Graphics

Hi Greg,

I ran into this exact problem when I was trying to set up a simulation
environment for the 66 MHz PCI bus.  Fortunately, the IBIS simulator I am
using
allows me to choose whether I want the buffer delays to come from a
simulation
into the standard load circuit from the IBIS model or from time values
which I
directly give to the simulator.  So what I did was use Spice to measure the
rise
and fall delays into their respective standard load circuits; I then gave
those
Spice generated numbers to my IBIS simulator.  Not an ideal solution, but a

workaround that worked good enough.

Unfortunately, this solution doesn't help you much if you can't directly
give
buffer delays to your simulator.  The ideal solution would be to enhance
the
IBIS spec to allow for a unique standard load circuit for both the rising
and
falling edges; that is, if this is a common problem.  Or is this pretty
much an
isolated case with the 66 MHz PCI spec?

Regards,

Tay Ansari
Sun Microsystems

We had a similar problem with a Motorola MPC750.  The L2 cache MAX timing
numbers are specified to a 20pF load and the MIN numbers to a 5pF load.
We were using ICX to analyze timing.  We looked at the output under no
load,
then at 20pF and 5pF.  The delta was measured to be 477ps.  We then
adjusted
the timing sheets in ICX so that the minimum allowed routing distance was
effectively increased by 477ps to compensate for the additional 'test'
load.
This allowed us to use a single IBIS model with Cref set at 20pF.  You may
be able to apply a similar 'trick' with the PCI driver and Vref.

David Haedge
Raytheon Systems Company

Greg,

You can put the two Vref numbers into the IBIS model and comment one of
them

out.  Unfortunately this means that you have to simulate things twice (with

most IBIS based simulators), but fortunately the waveforms are not effected
by
this, only the flight time measurements.  So one of the simulations could
do

the falling edge measurements, and the other one the rising edge
measurements.
If you need more detail send me another EMAIL, and I will give you an
example.

Arpad Muranyi
Intel Corporation
============================================================================

A question came up here at IBM today that I could not answer.  Has anyone
run
into this?

The 66 MHz PCI bus spec has a different standard load for rising and
falling

edges.  (10 pF and 25 Ohms to gnd for rising OR 10 pF and 25 Ohms to Vcc
for

falling.)  As I read version 3.1 of IBIS, it only allows one value of Vref
per
[Model] keyword.  This seems to make the 66 MHz PCI driver unable to be
implemented in IBIS, at least if you want to do timing analysis.  I would
think
someone else probably encountered this already.  How did you get around it?
Or
am I missing something?

Much thanks in advance.

Greg Edlund
Advisory Engineer, AS/400 System Timing
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email-masked]

Syed Huq <[email-masked]> on 02/01/2001 11:32:09 PM

Please respond to Syed Huq <[email-masked]>

To:   [email-masked]
cc:
Subject:  PCI and IBIS

IBISgurus:

The PCI spec mentions of multiple Vmeas data points based on Rising edge
or Falling edge. Since IBIS has only one Vmeas for any Output/I_O etc, how
does the model provider spec the PCI Vmeas values ?

Regards,
Syed
Cisco Systems, Inc

---

From: "Muranyi, Arpad" <[email-masked]>
Date: Fri, 2 Feb 2001 07:53:42 -0800

The problem with Bob's response from two years ago is that
you can't swith between buffers with the model selector
for rising and another one for falling edge...

Arpad
==========================================================

-----Original Message-----
From: Gregory R Edlund [mailto:[email-masked]]
Sent: Friday, February 02, 2001 6:58 AM
To: Syed Huq
Cc: [email-masked]
Subject: Re: PCI and IBIS

Syed,

Greg Edlund
Advisory Engineer
Electrical Packaging

To All:

Bob Ross

Hi Greg,

Regards,

Tay Ansari
Sun Microsystems

David Haedge
Raytheon Systems Company

Greg,

Arpad Muranyi
Intel Corporation

Much thanks in advance.

Greg Edlund

To:   [email-masked]
cc:
Subject:  PCI and IBIS

IBISgurus:

Regards,
Syed
Cisco Systems, Inc