Subject: Re: IBIS ML comment

From: Scott McMorrow <[email-masked]>
Date: Thu, 19 Jul 2001 01:40:42 -0700

Stephen,

In addition in the simple_receiver model is used as
follows:

[Model] xyz
model_type simple_receiver
C_comp 3pF 2pF 4pF
R_pullup 50 47 55
[Supply Voltage] 3.3v 3.0v 3.6v
[Power Clamp]
| volts I(typ) I(min) I(max)
-3.3v
0.0v
0.5v
0.6v
1.0v
2.5v
3.3v
[Gnd Clamp]
| volts I(typ) I(min) I(max)
-3.3v 100ma 80ma 120ma
-2.5v
-1.0v
-0.6v
0.0v
3.3v
[End Model]

Now, there is an interesting problem here.  In the model definition for
simple_receiver, we have defined the nodal connections to power and
ground and input( pwr, gnd, input ).  However, when we get to the
instantiation of that model, these nodes are not carried through ... they
are implied!   This is very, very, very bad.  In fact, there is nothing that
explicitly maps the implied power and ground clamps to specific power
and ground nodes.

Power and ground clamp tables are 2-port elements.  As such, there
needs to be a definition for the connection of these ports.  We cannot
continue to leave these to be implied by IBIS-X.  We also cannot assume
a particular name for the ground and power ports.  Or that there will
only be two clamp curves maximum and just one I/O node.

In this model there are implied connections for all of these lines:

[Supply Voltage] 3.3v 3.0v 3.6v
[Power Clamp]
[Gnd Clamp]

What two nodes should the supply voltage be attached to?
What two nodes should the power clamp be attached to?
What two nodes should the ground clamp be attached to?
What happens when there are two input pins, such as on
a differential receiver?
They need to be explicitly defined and mapped to node names, since
implicit naming (as currently used in IBIS) will no longer work.

I suggest that I/V curves be considered as 2-port
elements, just like a resistor.  In this case, the model could be
more explicitly stated as follows:

[Define Model] simple_receiver (pwr, gnd, input)
capacitor         io_cap (input gnd) C=C_comp
resistor            term_res (input pwr) R=(R_pullup || open)
ivcurve             power_clamp (pwr input) PC=(Power_clamp || open)
ivcurve             ground_clamp (input gnd) GC=(Gnd_clamp || open)
powerSelector voltage_range (pwr gnd) VR=(Supply_voltage)

[End Model] simple_receiver

[Model] xyz
model_type simple_receiver
C_comp 3pF 2pF 4pF
R_pullup 50 47 55
[Supply Voltage] 3.3v 3.0v 3.6v
[Temp]    25 125 0
[Power Clamp] powerClampTable_xyz
[Gnd Clamp] groundClampTable_xyz
[End Model]

One could place the table in model using the "standard fashion"
or one could call a named table.

[Table] powerClampTable_xyz
| volts I(typ) I(min) I(max)
-3.3v
0.0v
0.5v
0.6v
1.0v
2.5v
3.3v
[End Table] powerClampTable_xyz

Since the tables are general, they can be used as a standard
matrix element to describe most anything.  And ... they are not
limited to min typ and max columns.  It is certainly possible to
extend the table to additional supply voltage and/or temperature
corners just by adding columns.

This sort of structure would now allow the same IV curves to
be shared by multiple models in a component or across
multiple components in a component family.  This makes sense
since many I/O's on a device are identical structures with
internal control signal differences (i.e. input, 3-state, I/O ...).

regards,

scott

Scott McMorrow wrote:

> Stephen,
>
> I've started reviewing the IBIS-X and ML specifications.
> As I have time, I will prepare a list of comments as I did
> for the ICM specification.
>
> For now, here is the first obivious issue:
>
> On page 10 there is an example of a receiver:
>
>
>      [Define Model] simple_receiver (pwr, gnd, input)
>      capacitor io_cap (output gnd) C=C_comp
>      resistor term_res (output pwr) R=(R_pullup || open)
>      …MORE NEEDED…
>      [End Model] simple_receiver
>
> Since there is no section 9 to define the [Define Model]
> block I am just guessing here, but ... since your input
> parameter list is:
>         pwr
>         gnd
>         input
>
> the reference to output does not make sense.  Shouldn't
> the model be:
>
> [Define Model] simple_receiver (pwr, gnd, input)
> capacitor io_cap (input gnd) C=C_comp
> resistor term_res (input pwr) R=(R_pullup || open)
> …MORE NEEDED…
> [End Model] simple_receiver
>
>
> regards,
>
> scott
>
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com